CA3140M Intersil, CA3140M Datasheet - Page 6

• Manufacturer Part Number: CA3140M
• Description: IC OP AMP BIMOS 4.5MHZ 8-SOIC
• Manufacturer: Intersil

Specifications of CA3140M

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 9 V/µs
• Gain Bandwidth Product: 4.5MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 4mA
• Current - Output / Channel: 40mA
• Voltage - Supply, Single/dual (±): 4 V ~ 36 V, ±2 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• -3db Bandwidth: -

Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140
includes an on chip phase compensating capacitor that is
sufficient for the unity gain voltage follower configuration.
Input Stage
The schematic diagram consists of a differential input stage
using PMOS field-effect transistors (Q
mirror pair of bipolar transistors (Q
resistors together with resistors R
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Q
effected with a 10kΩ potentiometer connected across
Terminals 1 and 5 and with its slider arm connected to Terminal
4. Cascode-connected bipolar transistors Q
constant current source for the input stage. The base biasing
circuit for the constant current source is described
subsequently. The small diodes D
protection against high voltage transients, e.g., static electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q
and its cascode connected load resistance provided by
bipolar transistors Q
sufficient for a majority of the applications is provided by C
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
terminal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q
whose base currents are “mirrored” to current flowing through
diode D
operating such that output Terminal 6 is sourcing current,
transistor Q
from the V+ bus (Terminal 7), via D
conditions, the collector potential of Q
permit the necessary flow of base current to emitter follower
Q
17
which, in turn, drives Q
2
17
in the bias circuit section. When the CA3140 is
, Q
18
18
functions as an emitter-follower to source current
) is established by transistors (Q
13
3
). Offset nulling, when desired, can be
, Q
4
. On-chip phase compensation,
18
.
6
2
3
11
7
, D
through R
, R
, Q
13
9
4
9
, Q
, D
12
, and R
is sufficiently high to
5
10
) functioning as load
2
provide gate oxide
) working into a
, Q
5
. The mirror pair
11
5
14
. Under these
are the
, Q
15
CA3140, CA3140A
)
13
1
.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q
sinking element. Transistor Q
with current fed by way of Q
turn, is biased by current flow through R
The dynamic current sink is controlled by voltage level sensing.
For purposes of explanation, it is assumed that output Terminal
6 is quiescently established at the potential midpoint between
the V+ and V- supply rails. When output current sinking mode
operation is required, the collector potential of transistor Q
driven below its quiescent level, thereby causing Q
decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor Q
thereby reducing the channel resistance of Q
consequence, there is an incremental increase in current flow
through Q
result, Q
the incremental change in output voltage caused by Q
sink current flows regardless of load; any excess current is
internally supplied by the emitter-follower Q
protection of the output circuit is provided by Q
driven into conduction by the high voltage drop developed
across R
conditions, the collector of Q
reduce the base current drive from Q
flow in Q
Bias Circuit
Quiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R
The function of the bias circuit is to establish and maintain
constant current flow through D
connected transistor mirror connected in parallel with the base
emitter junctions of Q
current sampling diode that senses the emitter current of Q
and automatically adjusts the base current of Q
maintain a constant current through Q
currents in Q
D
establishes the currents in transistors Q
Typical Applications
Wide dynamic range of input and output characteristics with
the most desirable high input impedance characteristics is
achieved in the CA3140 by the use of an unique design based
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply
applications, such as, for example, where one input is driven
below the potential of Terminal 4 and the phase sense of the
output signal must be maintained – a most important
consideration in comparator applications.
1
. Furthermore, current in diode connected transistor Q
16
18
11
20
sinks current from Terminal 6 in direct response to
to the short circuited load terminal.
under output short circuit conditions. Under these
, R
2
, Q
12
3
, Q
are also determined by constant current flow
21
1
, Q
, D
2
6
, and Q
, R
21
19
16
, R
7
21
, and the base of Q
diverts current from Q
1
is mirror connected to D
12
, Q
is displaced toward the V- bus,
3
. D
, and Q
6
, Q
17
1
6
, thereby limiting current
may be considered as a
, Q
8
14
13
16
and D
20
, zener D
8
and Q
18
, D
is the current
. Transistor Q
21
. Short circuit
2
19
. As a
2
6
. The base
. D
, which is
15
(via Q
16
17
.
8
1
, and R
. As a
, Q
4
is a diode
July 11, 2005
18
so as to
1
18
6
FN957.10
) to
. This
2
, R
20
13
to
6
, in
14
7
is
1
,
.
.