HFA1113IB Intersil, HFA1113IB Datasheet - Page 6

• Manufacturer Part Number: HFA1113IB
• Description: IC BUFFER 850MHZ 8-SOIC
• Manufacturer: Intersil

Specifications of HFA1113IB

• Amplifier Type: Buffer
• Number Of Circuits: 1
• Slew Rate: 2400 V/µs
• -3db Bandwidth: 850MHz
• Current - Input Bias: 25µA
• Voltage - Input Offset: 8000µV
• Current - Supply: 21mA
• Current - Output / Channel: 60mA
• Voltage - Supply, Single/dual (±): 9 V ~ 11 V, ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Gain Bandwidth Product: -

.
10µF
Limiting Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
5) of the amplifier. V
sets the lower clamp level. If the amplifier tries to drive the
output above V
output voltage at V
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (V
feedback amplifiers, there is a unity gain buffer (Q
IN
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
∞
OR 0Ω (A
0.1µF
(A
V
R
50Ω
FIGURE 3. EVALUATION BOARD LAYOUT
= +1)
1
V
= +2)
H
, or below V
+IN
-5V
H
1
2
3
4
H
or V
BOTTOM LAYOUT
sets the upper output limit, while V
TOP LAYOUT
L
(± the clamp accuracy),
1
L
H
H
, the clamp circuitry limits the
6
) circuitry. As with all current
V
and V
H
V
GND
8
7
6
5
L
OUT
L
V-
terminals (pins 8 and
GND
50Ω
0.1µF
V+
V
H
GND
X1
OUT
V
L
- Q
10µF
X2
L
+5V
)
HFA1113
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V
This current is mirrored onto the high impedance node (Z) by
Q
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by Q
quiescent value, the current flowing through -IN is reduced to
only that small current (-I
the final voltage.
Tracing the path from V
clamp voltage on the high impedance node. V
by 2V
Q
reaches a voltage equal to Q
and Q
V
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V
When the output is clamped, the negative input continues to
source a slewing current (I
output to the quiescent voltage defined by the input. Q
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:
I
As an example, a unity gain circuit with V
would have I
(R
Note that I
clamp limited.
+IN
CLAMP
H
X3
P5
-IN
G
. R
FIGURE 4. HFA1113 SIMPLIFIED V
-Q
P4
= ∞ because -IN is floated for unity gain applications).
begins to conduct whenever the high impedance node
- V
BE
1
N5
X4
provides a pull-up network to ensure functionality
and Q
OUT
= (V
). Thus, Q
(Q
, where it is converted to a voltage and fed to the
CC
Q
Q
N6
V-
V+
CLAMP
-IN
)/R
N1
P1
N4
Q
Q
will increase by I
and Q
F
P3
N3
- V
. Note that when the output reaches its
V-
+ V
300Ω
OUT CLAMPED
P5
Q
I
Q
CLAMP
= (2V - 1V)/300Ω + 2V/∞ = 3.33mA
N2
P2
-IN
P6
clamps node Z whenever Z reaches
V+
/R
H
) to set up the base voltage on Q
BIAS
V
-IN
to Z illustrates the effect of the
G
R
(INTERNAL)
-IN
CLAMP
G
Q
P5
Q
) required to keep the output at
N4
P4
Z
’s base voltage + 2V
CLAMP
Q
Q
)/300Ω + V
N5
) in an attempt to force the
P5
H
(INTERNAL)
CLAMP CIRCUITRY
+1
IN
when the output is
R
F
Q
Q
= 2V, and V
= 300Ω
N6
P6
-IN
H
50K
(30K
FOR V
/R
decreases
200Ω
G
L
.
R
July 11, 2005
BE
L
.
1
)
H
FN1342.6
P5
(Q
= 1V,
V
V
P5
H
OUT
P5
.