AD8066AR-REEL Analog Devices Inc, AD8066AR-REEL Datasheet - Page 22

• Manufacturer Part Number: AD8066AR-REEL
• Description: IC OPAMP VF R-R DUAL LN LP 8SOIC
• Manufacturer: Analog Devices Inc
• Series: FastFET™r

Specifications of AD8066AR-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053)
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 180 V/µs
• -3db Bandwidth: 145MHz
• Current - Input Bias: 3pA
• Voltage - Input Offset: 400µV
• Current - Supply: 6.6mA
• Current - Output / Channel: 30mA
• Voltage - Supply, Single/dual (±): 5 V ~ 24 V, ±2.5 V ~ 12 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Gain Bandwidth Product: -

AD8065/AD8066
THERMAL CONSIDERATIONS
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8066 dissipates
312 mW. This can lead to noticeable thermal effects, especially
in the small SOT-23-5 (thermal resistance of 160°C/W). V
temperature drift is trimmed to guarantee a maximum drift of
17 μV/°C, so it can change up to 0.425 mV due to warm-up
effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.
I
I
single 5 V supply.
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken not to exceed the
rated power dissipation of the package.
b
b
increases by a factor of 1.7 for every 10°C rise in temperature.
is close to five times higher at 24 V supplies as opposed to a
V
THRESHOLD
V
N
Q1
R1
S
Figure 56. Simplified Input Stage
Q2
OS
R2
Rev. J | Page 22 of 28
D3
R3
I
T1
R4
Q3
V
INPUT AND OUTPUT OVERLOAD BEHAVIOR
A simplified schematic of the AD8065/AD8066 input stage is
shown in Figure 56. This shows the cascoded N-channel JFET
input pair, the ESD and other protection diodes, and the
auxiliary NPN input stage that eliminates any phase inversion
behavior. When the common-mode input voltage to the amplifier
is driven to within approximately 3 V of the positive power supply,
the input JFET’s bias current turns off and the bias of the NPN
pair turns on, taking over control of the amplifier. The NPN
differential pair now sets the amplifier’s offset, and the input
bias current is now in the range of several tens of microamps.
This behavior is shown in Figure 32. Normal operation resumes
when the common-mode voltage goes below the 3 V from the
positive supply threshold.
The output transistors of the rail-to-rail output stage have
circuitry to limit the extent of their saturation when the output
is overdriven. This helps output recovery time. Output recovery
from a 0.5 V output overdrive on a ±5 V supply is shown in
Figure 24.
CC
D1
D2
Q4
R7
R6
I
T2
D4
R8
–V
S
R5
Q6
TO REST OF AMP
EE
Q5
V
P
Q7
VBIAS