AD8066AR-REEL Analog Devices Inc, AD8066AR-REEL Datasheet - Page 9

• Manufacturer Part Number: AD8066AR-REEL
• Description: IC OPAMP VF R-R DUAL LN LP 8SOIC
• Manufacturer: Analog Devices Inc
• Series: FastFET™r

Specifications of AD8066AR-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053)
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 180 V/µs
• -3db Bandwidth: 145MHz
• Current - Input Bias: 3pA
• Voltage - Input Offset: 400µV
• Current - Supply: 6.6mA
• Current - Output / Channel: 30mA
• Voltage - Supply, Single/dual (±): 5 V ~ 24 V, ±2.5 V ~ 12 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Gain Bandwidth Product: -

ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction temperature
(T
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8065/AD8066.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
The still air thermal properties of the package and PCB (θ
ambient temperature (T
package (P
The junction temperature can be calculated by
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, then the total drive power is V
which is dissipated in the package and some in the load (V
I
power is the drive power dissipated in the package.
OUT
AD8065WARTZ Only
J
(Soldering, 10 sec)
) on the die. The plastic encapsulating the die locally reaches
). The difference between the total drive power and the load
T
P
P
J
D
D
= T
=
=
Quiescent
(
V
D
A
) determine the junction temperature of the die.
S
+ (P
×
I
S
D
)
× θ
+
S
Power
). Assuming the load (R
⎛
⎜
⎝
JA
V
2
)
S
A
), and total power dissipated in the
×
+
V
R
OUT
(
Total
L
⎞
⎟
⎠
−
Drive
V
Rating
26.4 V
See Figure 3
V
1.8 V
−65°C to +125°C
−40°C to +85°C
−40°C to +105°C
300°C
OUT
R
EE
L
D
) is the sum of the
− 0.5 V to V
Power
2
S
/2 × I
L
) is referenced to
−
S
) times the
OUT
Load
CC
, some of
+ 0.5 V
Power
JA
OUT
),
)
Rev. J | Page 9 of 28
×
RMS output voltages should be considered. If R
V
V
If the rms signal levels are indeterminate, then consider the
worst case, when V
In single-supply operation with R
is V
Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduce
the θ
at the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC (125°C/W),
SOT-23 (180°C/W), and MSOP (150°C/W) packages on a
JEDEC standard 4-layer board. θ
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
ESD CAUTION
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
S
S
−, as in single-supply operation, then the total drive power is
× I
OUT
2.0
1.5
1.0
0.5
JA
P
OUT
0
D
. Care must be taken to minimize parasitic capacitances
–60
= V
=
.
(
V
S
/2.
S
MSOP-8
–40
×
I
S
SOT-23-5
) (
+
–20
OUT
AMBIENT TEMPERATURE (°C)
V
R
S
= V
4 /
L
)
0
2
S
/4 for R
SOIC-8
20
JA
L
referenced to V
values are approximations.
L
to midsupply.
40
AD8065/AD8066
60
L
is referenced to
80
S
−, worst case
100
JA
. Also,