ADM693ARZ Analog Devices Inc, ADM693ARZ Datasheet - Page 4

• Manufacturer Part Number: ADM693ARZ
• Description: IC SUPER MPU 4.4 100MA WD 16SOIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693ARZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Threshold Voltage: 4.4V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 4.5V To 5.5V
• Reset Type: Active-High / Active-Low
• Supply Current: 1mA
• Delay Time: 50ms
• Digital Ic Case Style: WSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM690–ADM695
Mnemonic
V
V
V
GND
RESET
WDI
PFI
PFO
CE
CE
BATT ON
LOW LINE
RESET
OSC SEL
OSC IN
WDO
CC
BATT
OUT
IN
OUT
Logic Output. RESET is an active high output. It is the inverse of RESET.
Function
Power Supply Input: +5 V Nominal.
Backup Battery Input. Connect to Ground if a backup battery is not used.
Output Voltage, V
can supply up to 100 mA to power CMOS RAM. Connect V
0 V. Ground reference for all signals.
Logic Output. RESET goes low if
1. V
2. V
3. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM690/ADM691/ADM694/ADM695 and 4.4 V for the ADM692 and
ADM693. RESET remains low for 50 ms (ADM690/ADM691/ADM692/ADM693) or 200 ms (ADM694/ADM695)
after V
serviced within its timeout period. The RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as
shown in Table I. The RESET output has an internal 3 A pull up, and can either connect to an open collector
Reset bus or directly drive a CMOS gate without an external pull-up resistor.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO
goes low. Connect PFI to GND or V
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The
comparator is turned off and PFO goes low when V
Logic Input. The input to the CE gating circuit. Connect to GND or V
Logic Output. CE
threshold. If V
Logic Output. BATT ON goes high when V
is internally switched to V
PNP transistor to increase the output current above the 100 mA rating of V
Logic Output. LOW LINE goes low when V
above the reset threshold.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 A internal pull up, (see Table I).
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watch-
dog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ (ADM695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.
CC
CC
CC
falls below the Reset Threshold
falls below V
returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is enabled but not
CC
is below the reset threshold, CE
OUT
CC
BATT
or V
is a gated version of the CE
BATT
CC
. The output typically sinks 35 mA and can directly drive the base of an external
is internally switched to V
PIN FUNCTION DESCRIPTION
OUT
when not used.
OUT
CC
falls below the reset threshold. It returns high as soon as V
is internally switched to the V
OUT
–4–
IN
CC
signal. CE
is forced high. See Figures 5 and 6.
is below V
OUT
OUT
depending on which is at the highest potential. V
OUT
BATT
to V
tracks CE
CC
.
OUT
if V
OUT
if not used.
OUT
IN
BATT
.
when V
and V
input. It goes low when V
BATT
CC
is above the reset
are not used.
CC
rises
OUT
OUT
REV. A