ADM690AN Analog Devices Inc, ADM690AN Datasheet - Page 13
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ADM690AN
Manufacturer Part Number
ADM690AN
Description
IC SUPERVISOR MPU 4.65 WD 8DIP
Manufacturer
Analog Devices Inc
Type
Battery Backup Circuitr
Datasheet
1.ADM694ANZ.pdf
(16 pages)
Specifications of ADM690AN
Rohs Status
RoHS non-compliant
Number Of Voltages Monitored
1
Output
Push-Pull, Totem Pole
Reset
Active Low
Reset Timeout
35 ms Minimum
Voltage - Threshold
4.65V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Number Of Elements
1
Monitored Voltage 1 (typ)
4.75 to 5.5V
Threshold Voltage 1 (max)
4.73V
Watchdog Timer
Yes
Chip Enable Signals
Yes
Reset Active Time
70ms
Package Type
PDIP
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.5V
Reset Threshold Voltage (max)
4.73V
Reset Threshold Voltage (min)
4.5V
Family Name
ADM690
Power Dissipation
400mW
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Power Fail Detection
Yes
Mounting
Through Hole
Pin Count
8
Supply Current
1.95mA
Battery Backup Switching
Yes
Manual Reset
No
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADM690AN
Manufacturer:
AD
Quantity:
5 510
Part Number:
ADM690AN
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Reset Output
The internal voltage detector monitors V
RESET output to hold the microprocessor’s Reset line low
when V
timer holds RESET low for 50 ms (200 ms for the ADM695)
after V
repeated toggling of RESET even if the 5 V power drops out
and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for mi-
croprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. The power-up RESET pulse lasts 50 ms (200 ms for the
ADM695) to allow for this oscillator start-up time. If a different
reset pulse width is required, then a capacitor should be con-
nected to OSC IN or an external clock may be used. Please refer
to Table I and Figure 4. The manual reset switch and the 0.1 F
capacitor connected to the reset line can be omitted if a manual
reset is not needed. An inverted, active high, RESET output is
also available.
Power Fail Detector
The +5 V V
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R
processor will have the time when V
to save data into RAM. An earlier power fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.
REV. A
Figure 24. ADM691/ADM693/ADM695 Typical Application
INPUT POWER
+5V
R
R
1
2
BATTERY
CC
CC
NC
3V
rises above 4.65 V (4.4 V for ADM693). This prevents
is below 4.65 V (4.4 V for ADM693). An internal
CC
0.1 F
power line is monitored via a resistive potential
V
GND
OSC IN
OSC SEL
LOW LINE WDO
SYSTEM STATUS
PFI
V
BATT
INDICATORS
CC
ADM691
ADM693
ADM695
BATT
ON
RESET
CE
V
CE
PFO
OUT
WDI
OUT
IN
CC
falls from 4.8 V to 4.65 V
RESET
CC
0.1 F
and generates a
1
ADDRESS
and R
DECODE
CMOS
RAM
0.1 F
2
, the micro-
I/O LINE
NMI
RESET
A0–A15
P
–13–
RAM Write Protection
The ADM691/ADM693/ADM695 CE
Select inputs of the CMOS RAM. CE
as V
If V
pendent of the logic level at CE
cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
Watchdog Timer
The microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 sec-
onds to verify proper software execution. If a hardware or soft-
ware failure occurs such that WDI not toggled, the ADM691/
ADM693 will issue a 50 ms (200 ms for ADM695) RESET
pulse after 1.6 seconds. This typically restarts the micro-
processor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4.
The WATCHDOG OUTPUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low, it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI
unconnected.
The RESET output has an internal 3 A pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
CC
CC
falls below the reset threshold, CE
is above the 4.65 V (4.4 V for ADM693) reset threshold.
ADM690–ADM695
IN
. This prevents the micropro-
OUT
OUT
OUT
follows CE
line drives the Chip
goes high, inde-
IN
as long