X40020S14Z-A Intersil, X40020S14Z-A Datasheet - Page 3

• Manufacturer Part Number: X40020S14Z-A
• Description: IC VOLTAGE MONITOR DUAL 14-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40020S14Z-A

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 2.9V, 4.6V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low V
from low voltage conditions, resetting the system
when V
RESET/RESET is active until V
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V
and connects V
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
PIN CONFIGURATION
PIN DESCRIPTION
Pin
1
2
3
4
5
6
CC
CC
LOWLINE
RESET/
detection circuitry protects the user’s system
V2MON
V2FAIL
RESET
Name
WDO
MR
falls below the minimum V
OUT
LOWLINE
V2MON
RESET
V2FAIL
WDO
to whichever is higher. This pro-
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
goes HIGH when V2MON exceeds V
V2 Voltage Monitor Input. When the V2MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
not used.
Early Low V
When
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
resistor.
RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever
V
grammed time period (t
for t
RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever
V
grammed time period (t
for t
V
MR
SS
CC
CC
PURST
PURST
14-Pin SOIC, TSSOP
falls below V
falls below V
3
V
1
2
3
4
5
6
7
CC
X40020
thereafter.
thereafter.
> V
CC
CC
CC
TRIP1
Detect. This open drain output signal goes LOW when
returns to proper
TRIP1
TRIP1
14
13
12
11
10
with V
9
8
, this pin is pulled high with the use of an external pull up resistor.
TRIP1
PURST
PURST
voltage or if manual reset is asserted. This output stays active for the pro-
voltage or if manual reset is asserted. This output stays active for the pro-
V
BATT-ON
V
V
WP
SCL
SDA
BATT
CC
OUT
BATT
point.
) on power-up. It will also stay active until manual reset is released and
) on power-up. It will also stay active until manual reset is released and
X40020, 40021
input
TRIP2
. There is no power-up reset delay circuitry on this pin.
50mA from V
switches to V
voltage threshold and V
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Function
LOWLINE
V2MON
V2FAIL
RESET
WDO
V
MR
SS
14-Pin SOIC, TSSOP
PURST
CC
1
2
3
4
5
6
7
BATT
X40021
to 250µA from V
thereafter. It has an internal pull up
when V
BATT
14
13
12
11
10
9
8
TRIP2
CC
V
CC
.
V
BATT-ON
V
V
WP
SCL
SDA
drops below the low V
CC
OUT
BATT
voltage, V2FAIL goes
< V
BATT
TRIP1
. The device only
SS
.
or
TRIP2
V
CC
May 17, 2006
when
and
FN8112.1
CC
™