X40030S14Z-BT1 Intersil, X40030S14Z-BT1 Datasheet
X40030S14Z-BT1
Specifications of X40030S14Z-BT1
Related parts for X40030S14Z-BT1
X40030S14Z-BT1 Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. FN8114.2 ...
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Block Diagram V3MON V2MON DATA SDA REGISTER WP COMMAND DECODE TEST AND CONTROL LOGIC SCL V CC (V1MON) 2 X40030, X40031, X40034, X40035 + V TRIP3 V3 MONITOR - V LOGIC CC V2MON MONITOR V TRIP2 LOGIC - ...
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... X40030S14Z-B X40030S ZB (Note 2) X40030S14I-B X40030S IB X40030S14IZ-B X40030S ZIB (Note 2) X40030V14-B X4003 0VB X40030V14I-B X4003 0VIB X40030S14-A X40030S A X40030S14Z-A X40030S ZA (Note 2) X40030S14I-A X40030S IA X40030S14IZ-A X40030S ZIA (Note 2) X40030V14-A X4003 0VA X40030V14I-A X4003 0VIA PART NUMBER WITH RESET X40035S14-A X40035S A 1.3 to 5.5 ...
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... These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020 ...
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A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the ...
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Pinouts X40030, X40034 (14 LD SOIC, TSSOP) TOP VIEW V2FAIL 1 14 V2MON 2 13 LOWLINE RESET Pin Descriptions PIN NAME 1 V2FAIL V2 Voltage Fail ...
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Principles of Operation Power-on Reset Applying power to the X40030, X40031, X40034, X40035 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. • It prevents the system microprocessor from starting to operate with ...
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V TRIPX WDO 0 SCL SDA A0h Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and ...
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The new V voltage to be applied to VXMON will now TRIPX be: V (desired) – (V (actual) – V TRIPX TRIPX Note: This operation does not corrupt the memory array. Setting a Lower V Voltage (x= TRIPx ...
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X40030, X40031, X40034, X40035 NO NEW V APPLIED = X OLD V APPLIED + | ERROR | X NO – ERROR < MDE FIGURE PROGRAMMING TRIPX DESIRED V < TRIPX PRESENT VALUE YES EXECUTE V RESET ...
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WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit ...
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MRF: Manual Reset Fail Bit (Volatile) The MRF bit will be set to “0” when Manual Reset input goes active. WDF: Watchdog Timer Fail Bit (Volatile) The WDF bit will be set to “0” when the WDO goes active. LV1F: ...
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SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER In the read mode, the device will transmit 8-bits of data, release the SDA line, then monitor the line for an acknowledge. ...
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S T SIGNALS A FROM THE R MASTER T SDA BUS SIGNALS FROM THE SLAVE Read Operation Random read operation allows the master to access any memory location in the array. Prior to issuing ...
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... Trip Point Voltage Range TRIP1 CC (Note 8) SECOND SUPPLY MONITOR I V2MON Current V2 15 X40030, X40031, X40034, X40035 Thermal Information Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Commercial Temperature Range 0°C to +75°C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS ) Read 0. ...
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DC Operating Characteristics Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER V V2MON Trip Point Voltage Range TRIP2 (Note V2FAIL RPD2 TRIP2 (Note 9) THIRD SUPPLY MONITOR I V3MON Current V3 V V3MON ...
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Equivalent AC Output Load Circuit For 2.06kΩ 4.6kΩ RESET SDA WDO 30pF 30pF AC Test Conditions Input pulse levels V CC Input rise and fall times 10ns Input and output timing levels V ...
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Timing Diagrams Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing START SCL SDA IN WP Write Cycle Timing SCL TH SDA 8 BIT OF LAST BYTE Nonvolatile Write Cycle Timing SYMBOL t ...
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Power Fail Timings V TRIPX [ [ V CC V2MON OR V3MON [ [ LOWLINE V2FAIL OR V3FAIL RESET/RESET/MR Timings V TRIP1 RESET V RVALID RESET MR Low ...
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Low Voltage and Watchdog Timings Parameters (@ +25°C, V SYMBOL t V ,V2MON, V3MON, Fall Time V2MON, V3MON, Rise Time Reset Valid V RVALID RESET/RESET Delay (activation only) ...
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V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h START VTRIP1, VTRIP2, VTRIP3 Programming Specifications PARAMETER t WDO Program Voltage Setup Time VPS t WDO Program Voltage Hold Time VPH t V Level Setup ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...