X40239S16I-AT1 Intersil, X40239S16I-AT1 Datasheet - Page 17

• Manufacturer Part Number: X40239S16I-AT1
• Description: IC VOLTAGE MON TRPL EE 16-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40239S16I-AT1

• Number Of Voltages Monitored: 3
• Output: Open Drain, Open Drain
• Reset: Active High/Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.75V, 2.2V, 2.95V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The master terminates the read operation by not
responding with an ACKNOWLEDGE and instead
issuing a STOP condition (Refer to Figure 15).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In
this case, the device sets the address pointer to that of
the Address Byte, and then goes into standby mode
after the STOP bit. All bus activity will be ignored until
another START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
Signals from
the Master
Signals from
the Slave
SDA Bus
Signals from
the Slave
Signals from
the Master
SDA Bus
17
0 0 0
S
a
Address
t
r
t
Figure 16. Sequential EEPROM Read Sequence
Slave
Figure 15. Random EEPROM Address Read Sequence
1
0 1 0 0 0 0
X40231, X40233, X40235, X40237, X40239
1
Address
C
A
K
Slave
“Dummy” Write
Data
0
(1)
A
C
K
WRITE Operation
Address Byte
A
C
K
Data
A
C
K
(2)
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X4023x con-
tinues to output a Data Byte for each ACKNOWL-
EDGE received. The master terminates the read
operation by not responding with an ACKNOWLEDGE
and instead issuing a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through the entire memory contents to be serially read
during one operation. At the end of the address space
the counter “rolls over” to address 00h and the device
continues to output data for each ACKNOWLEDGE
received (Refer to Figure 16).
S
a
r
t
t
1 0 1 0 0 0 0
Address
Slave
A
C
K
(n is any integer greater than 1)
1
READ Operation
Data
(n-1)
C
A
K
Data
C
A
K
Data
S
o
p
(n)
t
April 11, 2005
S
o
p
t
FN8115.0