X40430S14I-B Intersil, X40430S14I-B Datasheet - Page 6

• Manufacturer Part Number: X40430S14I-B
• Description: IC VOLT MON TRPL EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40430S14I-B

• Number Of Voltages Monitored: 3
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.7V, 2.6V, 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATION
PIN DESCRIPTION
Pin
10
11
12
13
14
1
2
3
4
5
6
7
8
9
LOWLINE Early Low V
V2MON
RESET/
V3MON
V2FAIL
RESET
V3FAIL
Name
WDO
SDA
SCL
V
V
MR
WP
NC
SS
CC
LOWLINE
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
HIGH when V2MON exceeds V
V2 Voltage Monitor Input. When the V2MON input is less than the V
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to V
V2MON comparator is supplied by V2MON (X40430, X40431) or by the V
V
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
ever V
grammed time period (t
t
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V
grammed time period (t
t
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10MΩ typical).
V3 Voltage Monitor Input. When the V3MON input is less than the V
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
V3MON comparator is supplied by the V3MON input.
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V
HIGH when V3MON exceeds V
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Supply Voltage
PURST
PURST
V2MON
CC
RESET
V2FAIL
V
> V
MR
NC
SS
CC
CC
thereafter.
thereafter.
TRIP1
14 Ld SOIC, TSSOP
falls below V
falls below V
6
X40430, X40434
1
2
3
4
5
6
7
CC
.
Detect. This CMOS output signal goes LOW when
X40430, X40431, X40434, X40435
TRIP1
TRIP1
14
13
12
11
10
PURST
PURST
9
8
voltage or if manual reset is asserted. This output stays active for the pro-
voltage or if manual reset is asserted. This output stays active for the pro-
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
) on power-up. It will also stay active until manual reset is released and for
) on power-up. It will also stay active until manual reset is released and for
CC
TRIP2
TRIP3
. There is no power-up reset delay circuitry on this pin.
. There is no power-up reset delay circuitry on this pin.
Function
LOWLINE
V2MON
V2FAIL
RESET
PURST
V
MR
NC
SS
14 Ld SOIC, TSSOP
thereafter.
X40431, X40435
1
2
3
4
5
6
7
V
TRIP2
TRIP3
CC
SS
SS
< V
14
13
12
11
10
CC
or
voltage, V2FAIL goes LOW.
voltage, V3FAIL goes LOW.
9
8
or
TRIP1
V
input (X40434, X40435).
V
CC
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
CC
CC
and goes high when
when not used. The
when not used. The
TRIP2
TRIP3
and goes
and goes
May 24, 2006
FN8251.1