DSP56311VF150R2 Freescale Semiconductor, DSP56311VF150R2 Datasheet

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... Figure 1). The DSP56311 performs 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. © Freescale Semiconductor, Inc., 1999, 2005. All rights reserved. Memory Expansion Area Program RAM 32 K × ...

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... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for , , , and Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56311 Technical Data, Rev. 8 pin is active when RESET Voltage Freescale Semiconductor ...

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... K × 24-bit 64 K × 24-bit 63 K × 24-bit 48 K × 24-bit 47 K × 24-bit *Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP) Freescale Semiconductor Table 1. DSP56311 Features Description Instruction X Data RAM Y Data RAM Cache Size ...

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... The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document. ...

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... Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register. When set, the ABE bit eliminates the required set-up and hold times for addition, DRAM access is not supported above 100 MHz. Freescale Semiconductor DSP56311 Functional Signal Groupings Functional Group ...

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... PB9 HA9 PB10 HA10 PB13 Double DS HRD/HRD PB11 HWR/HWR PB12 Double HR HTRQ/HTRQ PB14 HRRQ/HRRQ PB15 Port C GPIO PC[0–2] PC3 PC4 PC5 Port D GPIO PD[0–2] PD3 PD4 PD5 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2 Freescale Semiconductor ...

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... Ground—Connected to an internal device ground plane. Note: The user must provide adequate external decoupling capacitors for all GND connections. 1.3 Clock State During Signal Name Type EXTAL Input Input XTAL Output Chip-driven Freescale Semiconductor Table 1-2. Power Inputs Description power rail CCQL . CCQL . CCQL ...

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... Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when external memory spaces are not being accessed. DSP56311 Technical Data, Rev. 8 Signal Description CCP , GND, or left floating Signal Description Freescale Semiconductor . ...

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... Output Tri-stated WR Output Tri-stated TA Input Ignored Input Freescale Semiconductor Table 1-7. External Data Bus Signals State During Stop or Wait Last state: Data Bus—When the DSP is the bus master, D[0–23] are active-high, Input : Ignored bidirectional input/outputs that provide the bidirectional data bus for Output : external program and data memory accesses. Otherwise, D[0– ...

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... Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude waveform that is not usable externally by other devices. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... Input IRQD Input RESET Input Schmitt-trigger Input Freescale Semiconductor Table 1-9. Interrupt and Mode Control Reset Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. ...

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... HI function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus. Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Signal Description Freescale Semiconductor ...

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... PB13 Input or Output HRW Input HRD/HRD Input PB11 Input or Output Freescale Semiconductor Table 1-11. Host Interface (Continued) 1,2 Reset Ignored Input Host Address Input 0—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe— ...

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... Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Signal Description Freescale Semiconductor ...

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... Input/Output PC3 Input or Output SRD0 Input PC4 Input or Output Freescale Semiconductor Enhanced Synchronous Serial Interface 0 (ESSI0) Enhanced Synchronous Serial Interface 0 1,2 Reset Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0— ...

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... Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. DSP56311 Technical Data, Rev. 8 Signal Description Signal Description Freescale Semiconductor ...

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... PE0 Input or Output TXD Output PE1 Input or Output Freescale Semiconductor Enhanced Serial Synchronous Interface 1 (Continued) 1,2 Reset Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes ...

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... Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. TIO2 can be changed to output or configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2). DSP56311 Technical Data, Rev. 8 Signal Description Signal Description Freescale Semiconductor ...

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... Output TMS Input TRST Input DE Input/ Output Freescale Semiconductor Table 1-16. JTAG/OnCE Interface Reset Input Test Clock—A test clock input signal to synchronize the JTAG test logic. Input Test Data Input—A test data serial input signal for test instructions and data. ...

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... Signals/Connections 1-16 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. Power-up sequence: During power-up, and throughout the DSP56311 operation, V equal to V voltage. CC Freescale Semiconductor CAUTION Table 2-1. Absolute Maximum Ratings Symbol V CC ...

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... Table 2-2. Thermal Characteristics 1,2 1,3 1,3 1 DSP56311 Technical Data, Rev. 8 MAP-BGA Symbol Unit Value ° C/W θJA ° C/W θJMA ° C/W θJMA ° C/W θJMA ° C/W θJB ° C/W θJC ° Ψ 2 C/W JT ° Ψ 2 C/W JT Freescale Semiconductor ...

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... Periodically sampled and not 100 percent tested. = 3.3 V ± 0 CCQH CC 7. This characteristic does not apply to XTAL and PCAP. 8. Driving EXTAL to the low V IHX power consumption, the minimum V 0.9 × V and the maximum V CCQH Freescale Semiconductor Table 2-3. DC Electrical Characteristics Symbol ) CCS IHP 0.8 × IHX V IL ...

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... ET — C 0.51 × ET × — C PDF × DF/MF 0.53 × ET × — C PDF × DF/MF ET — C 0.51 × ET × — C PDF × DF/MF 0.53 × ET × — C PDF × DF/MF × PDF × ET — C DF/MF 2 × ET — — C Freescale Semiconductor ...

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... EXTAL EXTAL ILX 2 5 CLKOUT with PLL disabled CLKOUT with PLL enabled 6a Freescale Semiconductor Suggested Component Values MHz OSC R = 680 kΩ ± 10% Note: Make sure that ± 20% the PCTL Register: • XTLD (bit 16 Calculations were done for a 4/20 MHz crystal • ...

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... I CYC 13.33 ns 8.53 µs 6.7 ns 150 MHz Min Max 30 300 (580 × MF) − 100 (780 × MF) − 140 830 × MF 1470 × computed using the appropriate expression CCP Freescale Semiconductor ∞ ∞ ∞ ∞ Unit MHz pF pF ...

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... PLL is not active during Stop (PCTL Bit and Stop delay is not enabled (Operating Mode Register Bit • PLL is active during Stop (PCTL Bit (Implies No Stop Delay) Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 3 5 (WS + 3.75) × T (WS + 3.25) × T (WS + 3.5) × ...

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... T 36.7 — C Maximum: 12 × T — 80 × T — 53 × T — 53 × T — 80.0 C Maximum: 6 × T — 40 × T — 46 × T — 13 × T — 20.0 C Minimum: 4.25 × 2.0 30.3 — valid, and the EXTAL input valid. The specified timing CC Freescale Semiconductor Unit ...

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... RESET All Pins A[0–17] A[0–17 IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI Freescale Semiconductor 9 8 Reset Value Figure 2-3. Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-4. ...

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... V IL Operating Mode Select Timing 24 25 Recovery from Stop State Using IRQA 26 25 Recovery from Stop State Using IRQA Interrupt Service DSP56311 Technical Data, Rev IRQA, IRQB, IRQC, IRQD, NMI V IL First Instruction Fetch First IRQA Interrupt Instruction Fetch Freescale Semiconductor ...

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... Address valid to WR deassertion 108 Data valid to WR deassertion (data set-up time) 109 Data hold time from WR deassertion 110 WR assertion to data active Freescale Semiconductor DMA Source Address 29 First Interrupt Instruction Execution External Memory Access (DMA Source) Timing Table 2-8. SRAM Timing ...

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... C [2 ≤ WS ≤ 7] 2.5 × T − 4.0 12.7 — C [WS ≥ 8] 0.5 × T − 2.8 0.5 — C − 4.0 11.0 — C − 4.0 4.3 — ≤ WS ≤ 7] − 4.0 11.0 — C [WS ≥ 8] 1.5 + 3.2 — — Freescale Semiconductor Unit ...

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... A[0–17] AA[0– D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Freescale Semiconductor 100 113 116 105 104 Figure 2-10. SRAM Read Access 100 ...

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... DRAM Page Mode Timings, Three Wait States Symbol CAC t AA DSP56311 Technical Data, Rev. 8 Chip frequency (MHz) 120 1,2,3 100 MHz 4 Expression Min Max 4 × T 40.0 — C 3.5 × T 35.0 — × T − 5.7 — 14 × T − 5.7 — 24.3 C Freescale Semiconductor Unit ...

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... An expression is used to compute the number listed as the minimum or C maximum value listed, as appropriate. 5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page- access deassertion always occurs after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol t OFF t RSH t RHCP ...

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... C 3.5 × T − 4.0 31.0 — 1.25 × T − 4.3 8.2 — 4.5 × T − 4.0 41.0 — 3.25 × T − 5.7 — 26 0.0 — ns 0.75 × T – 1.5 6.0 — 0.25 × T — 2 equals PC and not t . OFF GZ Freescale Semiconductor ...

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... CAS Row A[0–17] Add WR RD D[0–23] Figure 2-13. RAS CAS Row A[0–17] Add WR RD D[0–23] Figure 2-14. Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out ...

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... T − 4.0 58.5 — 3.75 × T − 4.0 33.5 — 2.5 × T ± 4.0 21.0 29 1.75 × T ± 4.0 13.5 21 5.75 × T − 4.0 53.5 — 4.25 × T – 6.0 36.5 — 4.25 × T − 4.0 38.5 — Freescale Semiconductor ...

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... Use the expression to compute the maximum or minimum value listed (or both if the expression includes ± Either must be satisfied for read cycles. RCH RRH 5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol t RAH t ASC t CAH t AR ...

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... C 1.5 × T − 4.0 11.0 — 4.75 × T − 4.0 43.5 — 15.5 × T − 4.0 151.0 — × T − 5.7 — 134 0.0 — ns 0.75 × T – 1.5 6.0 — 0.25 × T — 2 and not t . OFF GZ Freescale Semiconductor ...

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... RAS CAS A[0–17 D[0–23] Figure 2-16. Freescale Semiconductor 157 162 163 165 167 169 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DRAM Out-of-Page Read Access DSP56311 Technical Data, Rev. 8 ...

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... DRAM Out-of-Page Write Access 157 162 163 190 170 165 189 177 Figure 2-18. DRAM Refresh Access DSP56311 Technical Data, Rev. 8 157 162 164 166 174 176 Column Address 175 180 186 195 Data Out 162 Freescale Semiconductor ...

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... DSP56300 components that are potential masters on the same bus asserted and is deasserted, another DSP56300 component may assume mastership at the same time. BB Therefore, some non-overlap period between one ensures that overlaps are avoided. Freescale Semiconductor Table 2-13. Asynchronous Bus Timings 250 250+251 Asynchronous Bus Arbitration Timing ...

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... T + 6.5 13.1 — C 6.5 — — 13.0 0.0 — 3.0 — 2.2 — 0 — 3.0 — 2.2 — 3.5 10.1 — C 1.5 × 3.5 13.4 — C Freescale Semiconductor Unit ...

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... RXDF or HREQ bits, or waiting for the assertion of the HREQ signal. 12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc). HACK H[0–7] HREQ Figure 2-20. Freescale Semiconductor 1,2,12 Host Interface Timings 1.8 V ± 0 – ...

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... H[7–0] 340 341 HA[2–0] 336 337 330 HCS 317 HRD 328 332 327 326 H[7–0] 340 341 DSP56311 Technical Data, Rev. 8 333 337 318 319 329 338 333 318 319 329 338 Freescale Semiconductor ...

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... HTRQ (double host request) Figure 2-23. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HREQ (single host request) HTRQ (double host request) Figure 2-24. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe Freescale Semiconductor HA[2–0] 336 337 331 HCS 336 ...

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... Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 336 322 HAS 323 317 HRD 334 335 327 329 HAD[7–0] Address 326 340 341 DSP56311 Technical Data, Rev. 8 337 337 318 319 328 Data 338 337 318 319 328 Data 338 Freescale Semiconductor ...

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... HREQ (single host request) HTRQ (double host request) Figure 2-27. HA[10–8] HAD[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-28. Write Timing Diagram, Multiplexed Bus, Double Data Strobe Freescale Semiconductor 336 322 HAS 323 336 HRW 320 HDS ...

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... C − 5.5 — 11.5 C — 32 8.0 14.7 — C 0.0 — 9.0 — 64 × T 427.0 — − 10.0 203.5 — /2 − 10.0 203.5 — /2 − 30.0 183.5 — /2 − 30.0 183.5 — determined by the SCI clock ACC Freescale Semiconductor Unit ...

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... SCLK (Output) 403 TXD RXD SCLK (Input) TXD RXD Figure 2-29. 1X SCLK (Output) TXD Figure 2-30. Freescale Semiconductor 400 402 401 404 Data Valid 405 406 Data Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid ...

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... Freescale Semiconductor Unit ...

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... Asynchronous mode (asynchronous implies that TXC and RXC are two different clocks internal clock, Synchronous mode (synchronous implies that TXC and RXC are the same clock bit length wl = word length wr = word length relative Freescale Semiconductor Table 2-16. ESSI Timings (Continued Symbol ...

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... Normal mode, the output flag state is asserted for the entire frame period. 2-34 430 432 446 447 450 454 454 452 First Bit 459 457 453 461 458 460 462 Figure 2-31. ESSI Transmitter Timing DSP56311 Technical Data, Rev. 8 451 455 Last Bit 456 461 See Note Freescale Semiconductor ...

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... Timer Timing No. Characteristics 480 TIO Low 481 TIO High = 3.3 V ± 0 1.8 V ± 0 Note: V CCQH CC TIO Figure 2-33. Freescale Semiconductor 430 431 432 433 434 437 439 First Bit 443 441 442 444 Figure 2-32. ESSI Receiver Timing Table 2-17. ...

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... Table 2-18. GPIO Timing Expression Minimum: 6.75 × pF. L 492 493 Valid 494 Figure 2-34. GPIO Timing DSP56311 Technical Data, Rev. 8 100 MHz Unit Min Max — 8.5 ns 0.0 — ns 8.5 — ns 0.0 — ns 67.5 — 490 491 Freescale Semiconductor ...

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... TRST set-up time to TCK low = 3.3 V ± 0 Notes CCQH CC 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Freescale Semiconductor is not available). Table 2-19. JTAG Timing Characteristics × 3); maximum 22 MHz 1.8 V ± 0 –40°C to +100 ° ...

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... Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid Test Access Port Timing Diagram DSP56311 Technical Data, Rev. 8 502 V M 503 V IH 505 V IH 509 Freescale Semiconductor ...

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... Response time when DSP56311 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time = 3.3 V ± 0 1.8 V ± 0 Note: V CCQH CC DE Freescale Semiconductor 513 512 Figure 2-38. TRST Timing Diagram Table 2-20. OnCE Module Timing Expression Max 22.0 MHz 1.5 × T 5.5 × × ...

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... Specifications 2-40 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... Packaging This section includes diagrams of the DSP56311 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56311 is available in a 196-pin molded array plastic-ball grid array (MAP-BGA) package. Freescale Semiconductor DSP56311 Technical Data, Rev 3-1 ...

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... D5 NC D12 CCD GND GND CCD GND GND A17 A16 D0 GND GND V A14 A15 CCQH GND GND A13 V A12 CCQL GND GND V A10 A11 CCA GND GND GND GND CCA GND GND CCA WR RD BCLK BCLK V AA0 A0 CCC AA1 NC Freescale Semiconductor ...

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... A11 A10 V GND CCA GND GND CCA GND CCA AA0 V CCC AA1 Figure 3-2. Freescale Semiconductor Bottom View D14 D16 D19 V D23 CCD D13 D15 D17 D20 D21 D12 V D18 V D22 CCD CCQL GND GND GND GND GND GND GND GND ...

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... GND D10 GND D11 GND D12 D1 D13 D2 D14 V CCD E1 STD0 or PC5 E2 V CCS E3 SRD0 or PC4 E4 GND E5 GND E6 GND E7 GND E8 GND E9 GND E10 GND E11 GND E12 A17 E13 A16 E14 D0 F1 RXD or PE0 F2 SC10 or PD0 F3 SC00 or PC0 F4 GND F5 GND Freescale Semiconductor ...

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... G7 GND G8 GND G9 GND G10 GND G11 GND G12 A13 G13 V CCQL G14 A12 H1 V CCQH H2 V CCQL Freescale Semiconductor Signal List by Ball Number (Continued) Ball Signal Name No. H3 SCK0 or PC3 H4 GND H5 GND H6 GND H7 GND H8 GND H9 GND H10 GND H11 GND H12 ...

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... PLL, other GND signals do not support individual P P1 DSP56311 Technical Data, Rev. 8 Ball Signal Name No H5, HAD5, or PB5 P3 H3, HAD3, or PB3 P4 H1, HAD1, or PB1 P5 PCAP P6 GND P1 P7 AA2/RAS2 P8 XTAL P9 V CCC P10 TA P11 BB P12 AA1/RAS1 P13 BG P14 NC Freescale Semiconductor ...

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... A7 J13 A8 J12 A9 J14 AA0 N13 AA1 P12 AA2 P7 AA3 N7 BB P11 BCLK M10 BCLK N10 BG P13 Freescale Semiconductor Table 3-2. Signal List by Signal Name Ball Signal Name No. BR N11 CAS N8 CLKOUT M9 D0 E14 D1 D12 D10 B11 D11 A11 D12 C10 D13 ...

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... GND L9 GND L10 GND L11 GND N6 P GND DSP56311 Technical Data, Rev. 8 Ball Signal Name No HA0 M3 HA1 M1 HA10 L1 HA2 M2 HA8 M1 HA9 M2 HACK/HACK J1 HAD0 M5 HAD1 P4 HAD2 N4 HAD3 P3 HAD4 N3 HAD5 P2 HAD6 N1 HAD7 N2 HAS/HAS M3 HCS/HCS L1 HDS/HDS J3 HRD/HRD J2 HREQ/HREQ K2 HRRQ/HRRQ J1 HRW J2 HTRQ/HTRQ K2 HWR/HWR J3 Freescale Semiconductor ...

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... M2 PB11 J2 PB12 J3 PB13 L1 PB14 K2 PB15 J1 PB2 N4 PB3 P3 PB4 N3 PB5 P2 PB6 N1 PB7 N2 PB8 M3 PB9 M1 PC0 F3 PC1 D2 PC2 C1 Freescale Semiconductor Signal List by Signal Name (Continued) Ball Signal Name No. PC3 H3 PC4 E3 PC5 E1 PCAP P5 PD0 F2 PD1 A2 PD2 B2 PD3 G1 PD4 B1 PD5 C2 PE0 F1 PE1 G3 PE2 G2 PINIT D1 RAS0 ...

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... Packaging 3.2 MAP-BGA Package Mechanical Drawing Figure 3-3. DSP56311 Mechanical Information, 196-pin MAP-BGA Package 3-10 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from R performance is adequate, a system-level model may be appropriate. A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. Freescale Semiconductor , in ° C can be obtained from this equation: J × ) ...

Page 72

... T – has been defined – CAUTION this high-impedance circuit. pin. and V CC DSP56311 Technical Data, Rev )/P . This value gives a better estimate pin on the DSP and from the V CC and V GND CC . GND Freescale Semiconductor pins ...

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... Where node/pin capacitance V = voltage swing f = frequency of node/pin toggle For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4. Freescale Semiconductor and circuits. GND , , ). TMS and V GND ...

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... MHz, this skew is between − 1.4 ns and +3.2 ns. 4-4 – × × × 3 5.48 mA max) value reflects the typical possible switching of the internal buses on best- ⁄ ⁄ ( MHz = I – – typF2 typF1 DSP56311 Technical Data, Rev value CCItyp and for a EXTAL CLKOUT Freescale Semiconductor ...

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... PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. Freescale Semiconductor DSP56311 Technical Data, Rev. 8 PLL Performance Issues ...

Page 76

... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-6 is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56311 Technical Data, Rev For small MF (MF < 10) CLKOUT is slow EXTAL Freescale Semiconductor ...

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... Freescale Semiconductor Typical Power Consumption ; Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL program memory starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address ; BCR: Area w.s (SRAM) ...

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... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 Freescale Semiconductor DSP56311 Technical Data, Rev. 8 A-3 ...

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... YDAT_END ;************************************************************************** ; ; EQUATES for DSP56311 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** A-4 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... M_HF1 EQU $4 ; HPCR bits definition M_HGEN EQU $0 M_HA8EN EQU $1 M_HA9EN EQU $2 M_HCSEN EQU $3 Freescale Semiconductor ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ...

Page 82

... Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE) ; Transmitter Empty ; Transmit Data Register Empty ; Receive Data Register Full ; Idle Line Flag ; Overrun Error Flag ; Parity Error ; Framing Error Flag ; Received Bit 8 (R8) Address DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 83

... M_OF0 EQU 0 M_OF1 EQU 1 M_SCD EQU $1C M_SCD0 EQU 2 M_SCD1 EQU 3 M_SCD2 EQU 4 M_SCKD EQU 5 Freescale Semiconductor ; Clock Divider Mask (CD0-CD11) ; Clock Out Divider ; Clock Prescaler ; Receive Clock Mode Source Bit ; Transmit Clock Source Bit ; SSI0 Transmit Data Register 0 ; SSIO Transmit Data Register 1 ...

Page 84

... Receive Data Register Full ; SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Bits Mask B (TS16-TS31) ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Bits Mask B (RS16-RS31) ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 85

... M_T0L1 EQU 9 ;------------------------------------------------------------------------ ; ; EQUATES for TIMER ; ;------------------------------------------------------------------------ Freescale Semiconductor ; IRQA Mode Mask ; IRQA Mode Interrupt Priority Level (low) ; IRQA Mode Interrupt Priority Level (high) ; IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ...

Page 86

... Direction Bit ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag ; Prescaler Source Mask ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ; Timer Control 3 ; DMA Status Register ; DMA Offset Register 0 ; DMA Offset Register 1 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 87

... M_DAM2 EQU 6 M_DAM3 EQU 7 M_DAM4 EQU 8 M_DAM5 EQU 9 M_D3D EQU 10 Freescale Semiconductor ; DMA Offset Register 2 ; DMA Offset Register 3 ; DMA0 Source Address Register ; DMA0 Destination Address Register ; DMA0 Counter ; DMA0 Control Register ; DMA1 Source Address Register ; DMA1 Destination Address Register ; DMA1 Counter ...

Page 88

... EFCOP ALU Control Register ; EFCOP Data Base Address ; EFCOP Coefficient Base Address ; EFCOP Decimation/Channel Register ; PLL Control Register ; Division Factor Bits Mask (DF0-DF2) ; XTAL Range select bit ; XTAL Disable Bit ; STOP Processing State Bit ; PLL Enable Bit DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 89

... M_BNC EQU $F00 M_BAC EQU $FFF000 ; control and status bits in SR M_CP EQU $c00000 M_CA EQU 0 M_V EQU 1 Freescale Semiconductor ; PLL Clock Output Disable Bit ; PreDivider Factor Bits Mask (PD0-PD3) ; Bus Control Register ; DRAM Control Register ; Address Attribute Register 0 ; Address Attribute Register 1 ...

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... Bus Release Timing ; Address Tracing Enable bit in OMR. ; Stack Extension space select bit in OMR. ; Extensed stack UNderflow flag in OMR. ; Extended stack OVerflow flag in OMR. ; Extended WRaP flag in OMR. ; Stack Extension Enable bit in OMR. ;leave user definition as is. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... I_SI1RLS EQU I_VEC+$44 I_SI1TD EQU I_VEC+$46 I_SI1TDE EQU I_VEC+$48 I_SI1TLS EQU I_VEC+$4A ;------------------------------------------------------------------------ ; SCI Interrupts ;------------------------------------------------------------------------ I_SCIRD EQU I_VEC+$50 I_SCIRDE EQU I_VEC+$52 I_SCITD EQU I_VEC+$54 Freescale Semiconductor ; Hardware RESET ; Stack Error ; Illegal Instruction ; Debug Request ; Trap ; Non Maskable Interrupt ; IRQA ; IRQB ; IRQC ; IRQD ...

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... INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF A-16 ; SCI Idle Line ; SCI Timer ; Host Receive Data Full ; Host Transmit Data Empty ; Default Host Command ; EFilter input buffer empty ; EFilter output buffer full ; last address of interrupt vector space DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

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... Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Part Package Type Voltage DSP56311 1.8 V core Molded Array Process-Ball Grid 3.3 V I/O Array (MAP-BGA) How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: ...