DSP56311VF150R2 Freescale Semiconductor, DSP56311VF150R2 Datasheet - Page 3

• Manufacturer Part Number: DSP56311VF150R2
• Description: IC DSP 24BIT 150MHZ 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VF150R2

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 384KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/1.7/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Features
Table 1 lists the features of the DSP56311 device.
Freescale Semiconductor
Coprocessor (EFCOP)
Internal Peripherals
High-Performance
Internal Memories
Enhanced Filter
DSP56300 Core
Feature
:
• Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
• 192 × 24-bit bootstrap ROM
• 128 K × 24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
32 K × 24-bit
31 K × 24-bit
96 K × 24-bit
95 K × 24-bit
80 K × 24-bit
79 K × 24-bit
64 K × 24-bit
63 K × 24-bit
48 K × 24-bit
47 K × 24-bit
*Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP)
RAM Size
Program
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
with skew elimination
test access port (TAP)
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
six-channel home theater)
enabled
1024 × 24-bit
1024 × 24-bit
1024 × 24-bit
1024 × 24-bit
1024 × 24-bit
Instruction
Cache Size
DSP56311 Technical Data, Rev. 8
Table 1. DSP56311 Features
0
0
0
0
0
X Data RAM
48 K × 24-bit
48 K × 24-bit
16 K × 24-bit
16 K × 24-bit
24 K × 24-bit
24 K × 24-bit
32 K × 24-bit
32 K × 24-bit
40 K × 24-bit
40 K × 24-bit
Size*
Description
48 K × 24-bit
48 K × 24-bit
16 K × 24-bit
16 K × 24-bit
24 K × 24-bit
24 K × 24-bit
32 K × 24-bit
32 K × 24-bit
40 K × 24-bit
40 K × 24-bit
Y Data RAM
Size*
Instruction
disabled
disabled
disabled
disabled
disabled
enabled
enabled
enabled
enabled
enabled
Cache
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Switch
Mode
MSW1 MSW0
0/1
0/1
0
0
0
0
1
1
1
1
0/1
0/1
0
0
1
1
0
0
1
1
iii