MCIMX258CJM4A Freescale Semiconductor, MCIMX258CJM4A Datasheet
MCIMX258CJM4A
Specifications of MCIMX258CJM4A
Available stocks
Related parts for MCIMX258CJM4A
MCIMX258CJM4A Summary of contents
Page 1
... Residential gateway (smart metering) • Handheld scanners and printers • Electronic point-of-sale terminals • Patient-monitoring devices © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: IMX25CEC Rev. 8, 01/2011 MCIMX25 Package Information Plastic package Case 5284 mm, 0.8 mm Pitch Case 2107 mm, 0.5 mm Pitch ...
Page 2
... On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY. • Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included. • i.MX25 only supports Little Endian mode. i.MX25 Applications Processor for Consumer and Industrial Products, Rev Freescale Semiconductor ...
Page 3
... MCIMX253CJM4A i.MX257 MCIMX257CJM4A i.MX258 MCIMX258CJM4A i.MX257 MCIMX257CJN4A 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!) i ...
Page 4
... Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MCIMX258 ARM926EJ-S™ 400 MHz 16K I/D 128 KB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Freescale Semiconductor ...
Page 5
... Shared Domain SDMA Peripherals UART(3) CSPI(2) ADC/TSC Audio/Power Management Figure 1. i.MX25 Simplified Interface Block Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Ext. Graphics NAND Camera LCD Display 1 Accelerator Flash Sensor ARM ® Processor Domain (AP) LCDC / CSI ...
Page 6
... M3IF provides arbitration between multiple masters requesting access to the external memory. • Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to DDR2 and SDR interfaces. • NAND Flash controller (NFC) provides an interface to NAND Flash memories. • Wireless External Interface Memory controller (WEIM) interfaces to NOR Flash and PSRAM. Brief Description Freescale Semiconductor ...
Page 7
... Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Brief Description Each Enhanced Periodic Interrupt Timer (EPIT 32-bit set-and-forget timer that starts counting after the EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention ...
Page 8
... The SIM is designed to facilitate communication to SIM cards or pre-paid phone cards. The System JTAG Controller (SJC) provides debug and test control with maximum security. The SLCDC module transfers data from the display memory buffer to the external display device. peripheral ownership and access rights to an owned peripheral. Freescale Semiconductor ...
Page 9
... Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor The SSI is a full-duplex serial port that allows the processor to communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the inter-IC sound bus standard (I2S). The SSIs interface to the AUDMUX for flexible audio routing. ...
Page 10
... Determines the reference current for the USB PHY1 bandgap reference. An external 10 kΩ 1% resistor to GND is required. The output impedance of these signals is expected at 10 Ω recommended to also have on-board 33 Ω USBPHY2_DM USBPHY2_DP series resistors (close to the pins). i.MX25 Applications Processor for Consumer and Industrial Products, Rev Table 4. Signal Considerations (continued) Description Freescale Semiconductor ...
Page 11
... Core supply voltage (at 266 MHz) Core supply voltage (at 400 MHz) 1 Coin battery BAT_VDD I/O supply voltage, GPIO NFC,CSI,SDIO i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor CAUTION Table 5 may cause permanent Table 5. DC Absolute Maximum Ratings Symbol QV DD ...
Page 12
... DD_OSC24M V 1.4 — DD_PLL V 3.0 3.3 DD_tsc Vref 2 DD_tsc FUSEV 3.3 ± 5% — DD (program mode) V 1.0 — DD_ T –40 — A can be connected to DD_BAT Table 7 Freescale Semiconductor Max. Units 3.6 — 1.95 V 1.9 V 3.6 V 3.43 V 3.6 V 3.6 V 1. DD_tsc 3 ...
Page 13
... Table 10. Recommended External Reference Clock Specifications Voh Vol Frequency Tolerance Trise i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol I program I read ). program Table 8 ...
Page 14
... Tx 33.8 — — 0.6 Rx 120 — — Rx 252 — Tx 5.5 — 50 100 1 Stop/Sleep Run (266 MHz) Run (400 MHz) — Active @ 266 MHz On Off Off On Off On Off Off On Freescale Semiconductor Unit mA μA μA mA μA mA μA Active @ 400 MHz Off ...
Page 15
... Table 14. iMX25 Reduced Power Mode Current Consumption Power Group Power Supply BAT_VDD BAT_VDD i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Current Consumption for Power Modes Voltage Setting Doze Wait 5 μA 3.15 μ ...
Page 16
... Other power-up sequences may be possible; however, the above sequence has been verified and is recommended. • There is a 1-ms minimum time between supplies coming up, and a 1-ms minimum time between POR_B assert and deassert. i.MX25 Applications Processor for Consumer and Industrial Products, Rev CAUTION NOTE NOTE Freescale Semiconductor ...
Page 17
... NVCC_CRM reaches 3.3 V. Step 2 and step 4 order are critical for proper power-loss protection. This is to guarantee that POR is stable already at NVCC_CRM/QVDD power domain interface before QVDD is on, and POR instantly propagates to QVDD domain after QVDD is on. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Figure 2. Power-Up Sequence Diagram NOTE 17 ...
Page 18
... NVCC_EMI1, NVCC_EMI2 NVCC_CRM, NVCC_SDIO, NVCC_CSI, NVCC_NFC, NVCC_JTAG, NVCC_LCDC, NVCC_MISC MPLL_VDD, UPLL_VDD i.MX25 Applications Processor for Consumer and Industrial Products, Rev NOTE μs after all previous steps. NOTE NOTE Table 15. Power Consumption Voltage (V) 1.52 1.9 3.6 1.65 Max Current (mA) 360 30 110 20 Freescale Semiconductor ...
Page 19
... Core through I.D: 0.118 mm, Core through plating 0.016 mm. • Flag: Trace style with ground balls under the die connected to the flag i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 15. Power Consumption (continued) Voltage (V) 3.3 3.6 1.55 Table 12, for more details on the power modes ...
Page 20
... Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection NOTE Symbol Value Unit R 55 °C/W eJA R 33 °C/W eJA R 46 °C/W eJMA R 29 °C/W eJMA R 22 °C/W eJB R 13 °C/W eJCtop Ψ 2 °C/W JT Freescale Semiconductor ...
Page 21
... Minimum condition: BCS model, 1.95 V, and –40 °C. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: wcs model, 1.65 V, and 105 °C. 3. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: BCS model, 1.95 V, and 105 °C. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol Test Conditions Min. ...
Page 22
... V — — 150 nA 80 — — 1180 nA — — 1220 nA Typ. Max. Units — — V — 0.28 V — — mA — — mA — OVDD + 0.3 V — OVDD/2 – 0.125 V Freescale Semiconductor Notes 1 1 — — — Notes — — — ...
Page 23
... Table 20. GPIO DC Electrical Characteristics DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current for slow mode High-level output current for fast mode i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Test Min. Conditions — –0.3 — 0.25 Vtt — ...
Page 24
... OVDD — — 18.5 22 25.6 KΩ KΩ 85 100 120 KΩ 85 100 120 KΩ — — 100 μA 117 — 184 0.0001 0.0001 64 104 0.0001 0.0001 Freescale Semiconductor — — V — V — ...
Page 25
... AC Electrical Characteristics This section provides the AC parameters for slow and fast I/O. Figure 3 shows the load circuit for output. propagation waveforms. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol Test Conditions IIN OVDD = 3 OVDD = 3 OVDD = 1 OVDD = 1 ...
Page 26
... Output (at pad) i.MX25 Applications Processor for Consumer and Industrial Products, Rev 80% 20% PA1 50% tPLH 80% 50% 20% tTLH 50% tpv 50% Figure 6. Output Enable to Output Valid OVDD 80% 20% 0V PA1 VDD 50% 0V tPHL OVDD 80% 50% 20% 0V tTHL VDD 0 VDD OVDD Freescale Semiconductor ...
Page 27
... Output pad propagation tpo delay (high drive), 40%–60% Output pad propagation tpo delay (standard drive), 40%–60% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 21. Slow I/O AC Parameters Test Min. Capacitance Rise/Fall — — 40 3.0–3 0.95/0.84 3.0– ...
Page 28
... V/ns 0.84/1.23 1.19/1.58 0.54/0.73 0.91/1.20 0.35/0.50 0.60/0.80 0.76/1.10 1.17/1.56 0.41/0.62 0.63/0.86 0.34/0.49 0.58/0/79 0.34/0.49 0.36/0.49 0.40/0.59 0.60/0.83 0.21/0.32 0.32/0.44 0.20/0.30 0.34/0.47 0.11/0.17 0.20/0.27 Freescale Semiconductor ...
Page 29
... Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3 1.95 V (1.65–1.95 V range), and –40 °C. Input transition time from pad (20%–80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Test Min. Capacitance Rise/Fall 3.0– ...
Page 30
... V/ns 0.43/0.61 0.72/0.95 0.59/0.81 0.98/1.27 V/ns 0.34/0.50 0.56/0.72 0.40/0.55 0.66/0.87 V/ns 0.23/0.34 0.38/0.52 Freescale Semiconductor — ...
Page 31
... Table 23. Fast I/O AC Parameters for OVDD = 3.0 Parameter Duty Cycle Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Standard Drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Test Min. Symbol Condition Rise/Fall tdit ...
Page 32
... V/ns 1.26/1.70 1.78/2.39 V/ns 2 0.95/1.30 1.20/1.60 V/ns 0.63/0.87 108 250 mA/ns 113 262 82 197 mA/ 207 52 116 mA/ns 55 121 Freescale Semiconductor ...
Page 33
... Duty cycle Clock frequency Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor tpi 1.6pF 0.729/0.458 0.97/0.0649 1.404/0.97 tpi 1.6pF 1.203/0.938 1.172/1.187 1.713/1.535 tpi 1 ...
Page 34
... V/ns 2 0.72/0.81 1.66/1.68 0.62/0.70 1.03/1.05 V/ns 0.33/0.37 0.75/0.77 0.31/0.35 0.51/0.53 V/ns 0.16/0.18 0.38/0.39 171 407 mA/ns 3 183 432 100 232 mA/ns 106 246 50 116 mA/ns 52 123 0.11/0.13 0.16/0. 1.22/1.45 1.89/2.21 ns 2.04/2.27 2.69/3.01 ns Freescale Semiconductor ...
Page 35
... Output enable to output valid delay (max. drive), 50%–50% Output enable to output valid delay (high drive), 50%–50% Output enable to output valid delay (standard drive), 50%–50% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall Fduty — ...
Page 36
... V/ns 2 0.52/0.61 0.90/1.02 0.51/0.63 091/1.06 V/ns 0.36/0.42 0.63/0.67 0.37/0.44 0.65/0.72 V/ns 0.23/0.26 0.39/0.40 171 426 mA/ns 3 183 450 82 233 mA/ns 87 245 43 115 mA/ns 46 120 0.11/0.13 0.16/0. 1.40/1.34 2.25/2.16 ns 2.22/2.16 3.06/2.97 ns Max. Units OVDD+0.3 V 0.2 × OVDD V OVDD+0.6 V OVDD+0.6 V Freescale Semiconductor ...
Page 37
... Output enable to output valid delay (max. drive), 40%–60% Output enable to output valid delay (high drive), 40%–60% Output enable to output valid delay (standard drive), 40%–60% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 27. AC Parameters for SDRAM I/O Load Min. Symbol Condition Rise/Fall Fduty — ...
Page 38
... Max. Typ. Units Notes Rise/Fall — — 133 MHz 1 1.14/1.13 1.62/1. 2.13/2.09 3.015/2.7 7 1.71/1.68 2.39/2.22 ns 3.22/3.12 4.53/4.16 3.38/3.27 4.73/4.38 ns 6.38/6.23 9.05/8.23 Freescale Semiconductor ...
Page 39
... Output enable to output valid delay (standard drive), 40%–60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall ...
Page 40
... Max. Typ. Units Notes Rise/Fall — — 133 MHz — 0.80/0.72 1.19/1. 1.49/1.34 2.21/1.90 1.56/1.70 2.52/2. 2.07/2.19 3.29/3.24 1.60/1.75 2.49/2. 2.00/2.14 3.11/3.10 2.17/1.81 3.35/2. 2.56/2.29 3.35/2.54 2.13/1.86 3.38/2. 2.62/2.23 4.14/2.38 1.35/1.5 2.15/2.19 V/ns 2 0.72/0.81 1.12/1.16 Freescale Semiconductor ...
Page 41
... Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1 and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core (20%–80%). i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Load Min. ...
Page 42
... OVDD/2 + 0.25 VIL(ac) –0.3 Vid(ac) 3 Vix(ac) OVDD/2–0.175 4 Vox(ac) OVDD/2–0.125 1-Wire Memory Device OW2 OW3 OW1 Figure 7. 1-Wire RPP Timing Diagram Max. OVDD + 0.3 OVDD/2 – 0.25 0.5 OVDD + 0.6 OVDD/2 + 0.175 OVDD/2 + 0.125 “Presence Pulse” OW4 Freescale Semiconductor Units ...
Page 43
... OW6 Transmission Time Slot Figure 9 and Figure 10 show write 1 and read sequence timing, respectively. parameters (OW7–OW8) that are shown in the figure. 1-Wire bus (OWIRE_LINE) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol t RSTL t PDH t PDL t RSTH Table 33 describes the timing parameters (OW5– ...
Page 44
... OW9 Figure 10. Read Sequence Timing Diagram Table 34. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT t RELEASE Table 35. Timing Parameters Description Min. Typ. Max. Units μ μs 60 117 120 μs 15 — 45 Value/Contributing Factor Peripheral clock frequency 5.0 ns 4.6 ns 12.0 ns 8.5 ns 8 Freescale Semiconductor ...
Page 45
... PIO Mode Timing Parameters Figure 11 shows a timing diagram for PIO read mode. ADDR (See note 1) READ Data(15:0) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 35. Timing Parameters (continued) Description t1 t2r DIOR tA IORDY IORDY Figure 11. PIO Read Mode Timing ...
Page 46
... Write Data(15:0) i.MX25 Applications Processor for Consumer and Industrial Products, Rev Relation t1 t2w DIOR DIOW ton tA IORDY IORDY Figure 12. PIO Write Mode Timing Adjustable Parameter time_1 time_2r time_9 If not met, increase time_2 — time_ax time_pio_rdx time_1, time_2r, time_9 toff t1 Freescale Semiconductor Table 36 ...
Page 47
... Figure 14 show the timing for MDMA read and write modes, respectively. DMARQ ADDR (See note 1) DMACK DIOR READ Data(15:0) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Relation tgr tfr Figure 13. MDMA Read Mode Timing Table 37 Adjustable Parameter(s) ...
Page 48
... Applications Processor for Consumer and Industrial Products, Rev DIOW tm ton td1 tk td Figure 14. MDMA Write Mode Timing Relation tk1 tkjn toff Table 38 for details Adjustable Parameter(s) time_m time_d time_k time_d, time_k time_d — time_d time_k time_d, time_k time_jn — Freescale Semiconductor 3 ...
Page 49
... UDMA in-transfer. ADDR DMARQ DMACK DIOR DIOW IORDY DATA READ DATA WRITE buffer_en Figure 16. Timing for Host-Terminated UDMA In-Transfer i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor tack ADDR DMARQ DMACK tenv DIOR DIOW tc1 IORDY DATA READ tds ...
Page 50
... Applications Processor for Consumer and Industrial Products, Rev tmli tli5 tc1 tc1 tss1 tmli tds tdh tzah tzah Table 39. Value tack ton tdzfs tcvh toff Required Conditions time_ack time_env tskew3, ti_ds, ti_dh should be low enough T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh — Freescale Semiconductor ...
Page 51
... UDMA out-transfer. ADDR DMARQ DMACK DIOW DIOR DATA WRITE IORDY buffer_en Figure 19. Timing for Host-Terminated UDMA Out-Transfer i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor tack tenv tcyc tcyc ton tdzfs tdvs tdvh tdvs tli1 tack tss tcyc ...
Page 52
... The following subsections describe the CSI timing in gated and ungated clock modes. i.MX25 Applications Processor for Consumer and Industrial Products, Rev Table 40. Value Timing.” How to Meet? time_ack time_env time_dvs time_dvh time_cyc time_cyc — time_dzfs time_ss — — — — time_cvh — Freescale Semiconductor ...
Page 53
... Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge VSYNC HSYNC PIXCLK DATA[15:0] Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor ...
Page 54
... Min. Max. Units 67.5 — 1 — 1 — 1.2 — 10 — 10 — ± — 48 10% MHz describes the timing parameters P6 P5 Min. Max. Units 67.5 — 1 — 1.2 — 10 — 10 — ± — 48 10% MHz Freescale Semiconductor ...
Page 55
... Figure 23. CSPI Master Mode Timing Diagram SSn (input) t6’ SCLK (input) t10 t11 MISO t12 t13 MOSI Figure 24. CSPI Slave Mode Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor t2 t1 t2’ t1’ Table t7’ t5’ t3’ ...
Page 56
... T — per 2T — sclk 30 — per per 0 — — clkoL clkoH – clkiL clkiH 5 T ipg — clkoL clkoH clkiL clkiH T + 0.5 — ipg 0 — 0 — Freescale Semiconductor Units — — — — — ns — ns — — ...
Page 57
... SDRAM clock low-level width SD3 SDRAM clock cycle time SD4 CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor SD1 SD4 SD5 SD4 SD5 SD5 SD7 ...
Page 58
... Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID SD6 Address setup time SD7 Address hold time SD8 SDRAM access time i.MX25 Applications Processor for Consumer and Industrial Products, Rev Parameter Symbol Min. Max. tAS 2.0 — tAH 1.8 — tAC — 6.47 Freescale Semiconductor Unit ...
Page 59
... SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 26. SDR SDRAM Write Cycle Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Parameter SD1 SD3 SD11 SD5 SD12 SD7 ROW / BA Symbol Min. Max. tOH 1.2 — ...
Page 60
... SD2 SD3 SD10 ROW/BA Freescale Semiconductor Unit clock clock ns ns ...
Page 61
... ADDR BA CKE Don’t care Figure 28. SDRAM Self-Refresh Cycle Timing Diagram The clock continues to run unless CKE is low. Then the clock is stopped in low state. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol tCH tCL tCK tAS tAH 1 ...
Page 62
... SD18 SD17 Data Data Data Data SD17 SD18 Parameter Min. Max. Unit 1.8 — SD20 SD19 SD18 Data Data Data Data SD18 1 Symbol Min. Max. tDS 0.95 — tDH 0.95 — tDSS 1.8 — tDSH 1.8 — Freescale Semiconductor ns Unit ...
Page 63
... SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS) SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor SD22 SD21 Data ...
Page 64
... DDR3 SDRAM clock cycle time i.MX25 Applications Processor for Consumer and Industrial Products, Rev DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Table Parameter DDR2 51, “tlS, tlH Derating Values for DDR2-400 Symbol Min. Max. t 0.45 0. 0. Freescale Semiconductor Unit ...
Page 65
... Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Parameter CK, CK Differential Slew Rate 1.5 V/ns ΔtlH ΔtlS ΔtlH +94 +217 +124 +89 +209 +119 +83 +197 +113 ...
Page 66
... DSS t 0.2 — DSH t -0.25 0.25 DQSS t 0.35 — DQSH t 0.35 — DQSL Table 53, “DtDS1, 1,2,3 0.7 V/ns 0.6 V/ns 0.5 Vns ΔtD ΔtD ΔtD ΔtD ΔtD Δ Freescale Semiconductor Unit ns ns tCK tCK tCK tCK tCK 0.4 V/ns ΔtD Δ ...
Page 67
... DDR26 DQS output access time from SDCLK posedge 1 Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor DQS Single-Ended Slew Rate 63 — — ...
Page 68
... NFIO[7:0] Figure 35. Address Latch Cycle Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 34 through NF4 Freescale Semiconductor ...
Page 69
... Figure 37. Read Data Latch Cycle Timing Diagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
Page 70
... N/A tDHR N/A NOTE Table 56 describes the timing parameters Example Timing for ≈ NFC Clock 33 MHz Unit Min. Max. 28 — — — — 27.5 ns 620 — — — ns 12.5 — — — ns Freescale Semiconductor ...
Page 71
... WE4 Clock fall to address valid WE5 Clock rise/fall to address invalid WE6 Clock rise/fall to CSx_B valid WE7 Clock rise/fall to CSx_B invalid i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor WEIM Output Timing WE1 WE2 ... WE4 WE6 WE8 WE10 WE12 ...
Page 72
... Applications Processor for Consumer and Industrial Products, Rev (continued) Parameter NOTE Min. Max. Unit 3 — ns 1/2 BCLK — ns +2.63 6.9 — — ns 2.4 — — ns 7.2 — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
Page 73
... Last Valid Address ADDR CS[x] RW LBA OE EB[y] DATA Figure 40. Synchronous Memory Timing Diagram for Write Access— i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 56 for specific control parameter settings. WE4 V1 WE6 WE14 WE10 WE12 WE19 WE4 ...
Page 74
... WE22 WE22 WE19 WE19 V1 V1+2 Halfword Halfword WE18 WE18 WSC=2, SYNC=1, DOL=0 Address V1 WE15 WE24 WE22 WE17 V1 WE16 BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 WE5 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword WE5 WE7 WE9 WE13 WE17 V1+4 V1+8 V1+12 Freescale Semiconductor ...
Page 75
... M_DATA WE6 CS[x] RW LBA OE WE12 EB[y] Figure 44. Muxed A/D Mode Timing Diagram for Synchronous Read Access— i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor WE5 Address V1 WE16 Write WE15 WSC=7, LBA=1, LBN=1, LAH=1 WE5 Address V1 WE14 WE15 ...
Page 76
... Applications Processor for Consumer and Industrial Products, Rev Table 57 help to determine timing parameters relative to chip select (CS) WE31 Address V1 WE39 WE35 WE37 V1 WE43 MAXDI WE31 Addr. V1 WE32A WE40 WE39 WE35A WE37 WE32 Next Address WE40 WE36 WE38 WE44 D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
Page 77
... EB[y] DATA Figure 47. Asynchronous Memory Write Access CS[x] ADDR/ M_DATA RW LBA OE EB[y] Figure 48. Asynchronous A/D Mux Write Access i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 D(V1) Addr. V1 WE32A WE33 ...
Page 78
... CSA) –3 + (OEA + 3 + (OEA + RLBN + RLBN + RLBA + RLBA + ADH + 1 – ADH + 1 – CSA) CSA) — 3 – (OEN – CSN) 4 — (RBEA – CSA) 5 — 3 – (RBEN – CSN) — (LBA – CSA) — 3 – CSN Freescale Semiconductor Unit ...
Page 79
... DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Determination By Synchronous Measured 1 Parameters WE14 – ...
Page 80
... Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. i.MX25 Applications Processor for Consumer and Industrial Products, Rev first bit Figure 50. ESAI Transmit Timing 83 87 last bit 88 91 See Note Freescale Semiconductor ...
Page 81
... FSR (bit) out FSR (word) out Data in FSR (bit) in FSR (word) in Flags in Figure 52 shows the ESAI HCKT timing diagram. HCKT SCKT (output) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor first bit Figure 51. ESAI Receive Timing Diagram 95 96 Figure 52 ...
Page 82
... SSICC 4 × — — 2 × − 9.0 — 2 × — 2 × − 9.0 — 2 × — Table 58 and Table 59 describe Comments 3 Min. Max. Condition 30.0 — 30.0 — — — — 6 — 15 — — — 6 — 15 — — Freescale Semiconductor Unit ...
Page 83
... SCKT rising edge to FST out (wl) high 83 SCKT rising edge to FST out (wl) low 84 SCKT rising edge to data out enable from high impedance 85 SCKT rising edge to transmitter #0 drive enable assertion i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 3 Symbol Expression — — — — 5 — ...
Page 84
... Min. Max. Condition Unit — 18 — 13 — 21 — 16 — 14 — 9 2.0 — 18.0 — 2.0 — 18.0 — 4.0 — 5.0 — — 21.0 — ns — 14.0 — ns — 14 — 9 — — ns — 18.0 — ns — 18.0 — ns Table 61: Freescale Semiconductor ...
Page 85
... In normal-speed mode for MMC card, clock frequency can be any value between MHz. In high speed mode, clock frequency can be any value between MHz satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor SD4 SD2 SD5 CLK ...
Page 86
... FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. i.MX25 Applications Processor for Consumer and Industrial Products, Rev Table 62 describes the timing parameters (M1–M4) shown Table 62. MII Receive Signal Timing 1 M4 Min. Max. Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
Page 87
... MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL) Figure 57 shows MII asynchronous input timings. the figure. FEC_CRS, FEC_COL i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 63 describes the timing parameters (M5–M8) shown Table 63. MII Transmit Signal Timing ...
Page 88
... Applications Processor for Consumer and Industrial Products, Rev Min. 1.5 Table 65 describes the timing parameters (M10—M15) M14 M15 M10 M11 M12 M13 Min. 0 — 40% 40% Max. Unit — FEC_TX_CLK period Max. Unit — — ns — ns 60% FEC_MDC period 60% FEC_MDC period Freescale Semiconductor ...
Page 89
... M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 66 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 66 ...
Page 90
... Applications Processor for Consumer and Industrial Products, Rev Table 67. Tx Pin Characteristics Symbol Min. Typ. 2 — — 0 Table 68. Rx Pin Characteristics Symbol Min. Typ. 0.8 × Vcc 1 — — 0 OFFTXD 0. ONRXD OFFRXD Figure 60. FlexCAN Timing Diagram Max. Units 1 Vcc + 0.3 V — V Max. Units 1 Vcc V — Freescale Semiconductor ...
Page 91
... Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor V x 0.75 CC ...
Page 92
... Fast Mode Min. Max. Min. Max 2.5 4.0 - 0.6 4 3.45 0 0.9 4.0 - 0.6 4.7 - 1.3 4.7 - 0.6 3 250 - 100 4 1000 20+0.1C 300 300 20+0.1C 300 b - 400 - 400 Freescale Semiconductor START Unit μs μs - μ μs μs - μs - μ μ ...
Page 93
... A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Parameter ) b Standard Mode Unit Min ...
Page 94
... Wait between HSYNC and VSYNC rising edge T6 Wait between last data and HSYNC rising edge pixel clock period i.MX25 Applications Processor for Consumer and Industrial Products, Rev Description Table 71 Line n Line 1 T6 Min. Max. 22.5 1000 1 — 5 — 5 — 2 — 1 — Freescale Semiconductor and Unit ...
Page 95
... The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor T4 Figure 66. LCDC TFT Mode Timing Diagram Description Table 73 lists the PWM timing characteristics ...
Page 96
... ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816). i.MX25 Applications Processor for Consumer and Industrial Products, Rev Figure 67. PWM Timing Table 73. PWM Output Timing Parameter Minimum 1 0 12.29 9.91 — — — 8. Maximum Unit ipg_clk MHz — ns — ns 0.5 ns 0.5 ns 9.37 ns — ns Freescale Semiconductor ...
Page 97
... SIM RST rise time / fall time (SIMx_RSTy) 1 50% duty cycle clock, 2 With With With Cin = 30 pF, Cout = 30 pF, 5 With Cin = 30 pF, i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 1 /SI1 SI3 SI4 SI5 SI6 Figure 68. SIM Clock Timing Diagram Symbol ...
Page 98
... SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. i.MX25 Applications Processor for Consumer and Industrial Products, Rev RESPONSE Min. Max. — 200 400 40,000 Units clk cycles clk cycles Freescale Semiconductor ...
Page 99
... SIMx_DATAy_RX_TX is negated • SIMx_SVENy is negated Each of the above steps requires one CKIL period (usually 32 kHz). Power-down may be initiated by a SIM card removal detection may be launched by the processor. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 3 T1 Min. Max. — ...
Page 100
... SJC timing parameters (SJ1–SJ13) indicated in the SJ1 SJ2 VM VIL Figure 72. Test Clock Input Timing Diagram Min. Max. 0.9 × 1/Fckil 1.1 × 1/Fckil 1.8 × 1/Fckil 2.2 × 1/Fckil 2.7 × 1/Fckil 3.3 × 1/Fckil 0.9 × 1/Fckil 1.1 × 1/Fckil SJ2 VM SJ3 Freescale Semiconductor Unit ...
Page 101
... TDO (Output) TDO (Output) TDO (Output) Figure 74. Test Access Port Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid ...
Page 102
... Applications Processor for Consumer and Industrial Products, Rev. 8 102 SJ13 Figure 75. TRST Timing Diagram Table 78. SJC Timing Parameters All Frequencies Unit Min. Max. 1 100 — 40 — — — 50 — — 50 — — 50 — — 44 — 44 100 — 40 — Freescale Semiconductor ...
Page 103
... RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor tcss tcyc tds MSB trss RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 1, CSPOL = 0) ...
Page 104
... CSPOL=0) trss trsh tcyc tds tdh command data display data (This diagram shows the case CSPOL=1) Typ. Max. Units — — ns — — ns — 2641 ns — — ns — — ns — — ns — — ns — — ns — — ns Freescale Semiconductor ...
Page 105
... AUDn_TXFS (bl) (Output) AUDn_TXFS (wl) (Output) AUDn_TXD (Output) AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 78. SSI Transmitter with Internal Clock Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Min ± prop / 2) ( ± cyc prop / 2) ( ± cyc prop / 2) ( ± ...
Page 106
... Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pf Freescale Semiconductor ...
Page 107
... CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low SS47 Oversampling clock period i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor SS1 SS5 SS4 SS9 SS11 SS20 SS51 SS47 ...
Page 108
... Applications Processor for Consumer and Industrial Products, Rev. 8 108 Parameter SS22 SS25 SS26 SS27 SS31 SS37 SS44 Min. Max. 6.0 — — 3.0 6.0 — — 3.0 Table 83 describes the timing SS24 SS29 SS33 SS39 SS38 SS45 SS46 Freescale Semiconductor Unit ...
Page 109
... For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation). i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Parameter External Clock Operation Synchronous External Clock Operation Min ...
Page 110
... External Clock Operation Table 84 describes the timing parameters SS24 SS34 SS41 SS36 Min. Max. 81.4 — 36.0 — — 6.0 36.0 — — 6.0 –10.0 15.0 10.0 — –10.0 15.0 10.0 — — 6.0 — 6.0 10.0 — 2.0 — Freescale Semiconductor Unit ...
Page 111
... With a 250fF load edge (teoc) Valid data out delay after With a 250fF load eoc rise edge (tdata) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Conditions ADC — Analog Bias — Timing Characteristics — ...
Page 112
... Power Supply Requirements — — Touchscreen Interface — 3 Conversion Characteristics — Min. Typ. Max. Unit — — 2.1 mA 0.5 mA — — Ω 100 — 1500 Ω — — 10 — +/–0.75 — LSB — +/–2.0 — LSB — — +/–2 %FS Freescale Semiconductor ...
Page 113
... Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Figure 82. Start-up Sequence st ). The best way to guarantee this is to make the input multiplexer ...
Page 114
... ADC operation, including the idle cycles. If the conditions are not met power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 114 Freescale Semiconductor ...
Page 115
... UA1 Start TXD Bit 0 Bit 1 Bit (output) Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Possible Parity Bit ...
Page 116
... Bit Next Start STOP Bit 6 Bit 7 Par Bit Bit BIT UA2 UA2 Min. Max. 2 – 1/(16 1/F + 1/(16 baud_rate baud_rate × F × baud_rate baud_rate UA4 UA3 UA3 Possible Bit 5 Bit 6 Bit 7 Parity Bit Freescale Semiconductor Units — Units — STOP BIT ...
Page 117
... DAT_SE0 unidirectional, 6-wire mode • VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode The following subsections describe the timings for these four modes. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Symbol Min 1/F – T TIRbit ...
Page 118
... Applications Processor for Consumer and Industrial Products, Rev. 8 118 Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high US1 US4 US7/US8 Signal Description US2 US6 Freescale Semiconductor ...
Page 119
... USB_RCV Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Transmit USB_DAT_VP USB_SE0_VM Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Signal Name Direction Min. USB_DAT_VP Out USB_SE0_VM Out USB_TXOE_B ...
Page 120
... Tx VP data when USB_TXOE_B is low In (Rx) • data when USB_TXOE_B is high Out (Tx) • data when USB_TXOE_B low In (Rx) • data when USB_TXOE_B high In • Differential Rx data US14 Condition/ Max. Unit Reference Signal 51.0 % — 8.0 ns USB_TXOE_B 10.0 ns USB_TXOE_B Signal Description Freescale Semiconductor ...
Page 121
... Tx rise/fall time US21 Tx duty cycle US22 Tx high overlap US23 Tx low overlap US24 Enable delay US25 Disable delay i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor US4 US2 US5 Signal Name Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — ...
Page 122
... Tx VP data when USB_TXOE_B is low Out Tx VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high In Differential Rx data US30 US34 Condition/ Max. Unit Reference Signal — 3.0 ns — 3.0 ns +4.0 ns USB_SE0_VM +2.0 ns USB_DAT_VP Signal Description US32 US31 Freescale Semiconductor ...
Page 123
... Tx low overlap US36 Enable delay US37 Disable delay US38 Rx rise/fall time US39 Rx rise/fall time US40 Rx skew US41 Rx skew i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor US38 US40 US39 US41 Signal Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — ...
Page 124
... Dimensioning and tolerancing per ASME Y14.5M-1994. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 124 Signal Description Table 99 US16 US16 US17 US17 Min. Max. — 6.0 — 0.0 — 9.0 describes the timing Conditions/ Unit Reference Signal Figure 98: Freescale Semiconductor ...
Page 125
... Table 100. 17×17 mm Package Ground, Power Sense, and Reference Contact Assignments Contact Name BATT_VDD P10 FUSE_VDD T17 MPLL_GND U17 MPLL_VDD U18 NGND_ADC Y13 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 17×17 i.MX25 Production Package zzxz Contact Assignment 125 ...
Page 126
... K16 USBPHY1_VDDA_BIAS K19 USBPHY1_VSSA L19 USBPHY1_VSSA_BIAS J17 USBPHY2_VDD W18 USBPHY2_VSS W17 1 NVCC_DRYICE is a supply output. An external capacitor no less than 4 µF must be connected to it. A 4.7 µF capacitor is recommended. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 126 Contact Assignment Freescale Semiconductor ...
Page 127
... A21 C7 A22 A5 A23 A6 A24 B7 A25 A7 SD0 A12 SD1 C13 SD2 B13 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR ...
Page 128
... Keeper OUTPUT Low OUTPUT Low OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT Low OUTPUT High INPUT Keeper INPUT Keeper OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High Freescale Semiconductor ...
Page 129
... LD0 Y7 2 LD1 V8 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI1 GPIO EMI1 GPIO NFC GPIO EMI1 GPIO EMI1 DDR EMI1 DDR EMI1 DDR NFC GPIO NFC GPIO NFC GPIO ...
Page 130
... OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low INPUT 100Kohm Pull-Down INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper OUTPUT Low INPUT Keeper INPUT Keeper Freescale Semiconductor ...
Page 131
... KPP_ROW0 N4 KPP_ROW1 R1 KPP_ROW2 P3 KPP_ROW3 P2 KPP_COL0 P1 KPP_COL1 N3 KPP_COL2 N2 KPP_COL3 N1 FEC_MDC L1 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type CSI GPIO CSI GPIO CSI GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO ...
Page 132
... INPUT 100Kohm Pull-Down OUTPUT Low INPUT 100Kohm Pull-Down INPUT 47Kohm Pull-Up INPUT 47Kohm Pull-Up INPUT - INPUT 47Kohm Pull-Up INPUT 47Kohm Pull-Up INPUT 100Kohm Pull-Up ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - INPUT - INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down INPUT - Freescale Semiconductor ...
Page 133
... P12 OSC_BYP Y12 XP V14 XN U13 YP V13 YN W12 WIPER U14 INAUX0 U11 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type CRM GPIO CRM GPIO CRM GPIO CRM GPIO CRM GPIO CRM GPIO CRM GPIO ...
Page 134
... Applications Processor for Consumer and Industrial Products, Rev. 8 134 Power Rail I/O Buffer Type ADC ANALOG ADC ANALOG Contact Assignment B20 E17 H17 J19 M18 P20 U15 U16 V15 V16 V17 W14 Y2 Y14 Y17 Direction after Configuration 1 1 Reset after Reset ANALOG - ANALOG - Freescale Semiconductor ...
Page 135
... Package Ball Map Table 103 shows the i.MX25 17×17 package ball map. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Table 103. i.MX25 17×17 Package Ball Map 135 ...
Page 136
... Table 103. i.MX25 17×17 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 136 Freescale Semiconductor ...
Page 137
... Table 103. i.MX25 17×17 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 137 ...
Page 138
... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. • Parallelism measurement shall exclude any effect of mark on package’s top surface. Figure 99. 12×12 mm i.MX25 Production Package i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 138 Figure 99: Freescale Semiconductor ...
Page 139
... AA21, AB1, AB18, AB21, AB22, J11 QVDD G7, G13, H7, H13, H18, J18, N7, N8, R10, R15, R16, T9, T10, V10, REF AA14 UPLL_GND N16 UPLL_VDD M18 USBPHY1_UPLLV L21 DD USBPHY1_UPLLVS M19 S i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Contact Assignment 139 ...
Page 140
... L22 BIAS USBPHY1_VSSA K19 USBPHY1_VSSA_ K18 BIAS USBPHY2_VDD T16 USBPHY2_VSS W16 1 NVCC_DRYICE is a supply output. An external capacitor no less than 4 µF must be connected to it. A 4.7 µF capacitor is recommended. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 140 Contact Assignment Freescale Semiconductor ...
Page 141
... A20 B6 A21 D7 A22 A7 A23 E9 A24 B7 A25 D8 SD0 A13 SD1 D12 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 ...
Page 142
... Keeper INPUT Keeper OUTPUT Low OUTPUT Low OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT Low OUTPUT High INPUT Keeper INPUT Keeper OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High Freescale Semiconductor ...
Page 143
... D11 K5 D10 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI2 DDR EMI1 GPIO EMI1 GPIO NFC GPIO EMI1 GPIO EMI1 DDR EMI1 DDR EMI1 DDR NFC GPIO NFC GPIO NFC ...
Page 144
... OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low INPUT 100Kohm Pull-Down INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper OUTPUT Low Freescale Semiconductor ...
Page 145
... V1 UART2_TXD T4 UART2_RTS T2 UART2_CTS P5 SD1_CMD N22 SD1_CLK N21 SD1_DATA0 P22 SD1_DATA1 R22 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type CSI GPIO CSI GPIO CSI GPIO CSI GPIO CSI GPIO MISC GPIO MISC GPIO ...
Page 146
... Pull-Up INPUT 100Kohm Pull-Up INPUT 100Kohm Pull-Up INPUT 100Kohm Pull-Up OUTPUT Low INPUT 22Kohm Pull-Up OUTPUT High OUTPUT High OUTPUT Low INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down OUTPUT Low INPUT 100Kohm Pull-Down Freescale Semiconductor ...
Page 147
... R19 EXT_ARMCLK V22 UPLL_BYPCLK U21 VSTBY_REQ T21 3 VSTBY_ACK W22 POWER_FAIL T19 RESET_B U19 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor Power Rail I/O Buffer Type JTAG GPIO JTAG GPIO JTAG GPIO JTAG GPIO JTAG GPIO JTAG GPIO ...
Page 148
... Configuration 1 1 Reset after Reset INPUT 100Kohm Pull-Up OUTPUT Low INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down INPUT 100Kohm Pull-Down ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - Freescale Semiconductor ...
Page 149
... Signal Name NC_BGA_E4 NC_BGA_L4 4.8 i.MX25 12x12 Package Ball Map Table 107 shows the i.MX25 12×12 package ball map. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor E4 L4 Table 107. i.MX25 12×12 Package Ball Map Contact Assignment 149 ...
Page 150
... Table 107. i.MX25 12×12 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 150 Freescale Semiconductor ...
Page 151
... Table 107. i.MX25 12×12 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 151 ...
Page 152
... Bus Timing Parameters. Table 85, “Touchscreen ADC Electrical Specifications.” 37, the frequency specification has been 38, the frequency for NVCC_DRYICE signal. 13. 13. 125. 139. to include new row for WE19. to include Min and Max values of Pitch. 5, “DC Absolute Maximum Ratings.” Freescale Semiconductor 127. 141. ...
Page 153
... THIS PAGE INTENTIONALLY LEFT BLANK i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8 Freescale Semiconductor 153 ...
Page 154
... Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...