AT91SAM7S128C-MU-999 Atmel, AT91SAM7S128C-MU-999 Datasheet - Page 16
![IC MCU ARM7 128KB FLASH 64-VQFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT91SAM7S128C-MU-999
Manufacturer Part Number
AT91SAM7S128C-MU-999
Description
IC MCU ARM7 128KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S128C-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S128-MU-999
AT91SAM7S128-MU-999
AT91SAM7S128-MU-999
7. Processor and Architecture
7.1
7.2
7.3
16
ARM7TDMI Processor
Debug and Test Features
Memory Controller
AT91SAM7S Series Summary
• RISC processor based on ARMv4T Von Neumann architecture
• Two instruction sets
• Three-stage pipeline architecture
• Integrated EmbeddedICE
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
• Embedded Flash Controller
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
– ARM
– Thumb
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
– Embedded Flash interface, up to three programmable wait states
®
high-performance 32-bit instruction set
®
high code density 16-bit instruction set
™
(embedded in-circuit emulator)
6175IS–ATARM–30-Aug-10