MC9S08DV128CLH Freescale Semiconductor, MC9S08DV128CLH Datasheet - Page 186
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MC9S08DV128CLH
Manufacturer Part Number
MC9S08DV128CLH
Description
MCU 8BIT 128K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV128CLH
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV128CLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
To change from FEI clock mode to FBI clock mode, follow this procedure:
8.5.2
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor
of 1024, the DCO output (MCGOUT) frequency is 33.55 MHz at high-range. If DRS is cleared to 0, the
multiplication factor is halved to 512, and the resulting DCO output frequency is 16.78 Mhz at mid-range.
Setting the DMX32 bit in MCGT to 1 increases the FLL multiplication factor to allow the 32.768 kHz
reference to achieve its maximum DCO output frequency. When the DRS bit is set, the 32.768 kHz
186
5. Write to the MCGT register to determine the DCO output (MCGOUT) frequency range.
6. Wait for the LOCK bit in MCGSC to become set, indicating that the FLL has locked to the new
1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
— By default, with DMX32 (bit 5) cleared to 0, the FLL multiplier for the DCO output is 1024.
— When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that
— When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that
multiplier value designated by the DRS and DMX32 bits.
system clock source.
reference clock has been appropriately selected.
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
external clock source has finished its initialization cycles and stabilized. Typical crystal startup
times are given in Appendix A, “Electrical Characteristics”.
moving on.
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock
in FBE mode.
For greater flexibility, if a mid-range FLL multiplier of 512 is desired instead, clear the DRS
bit (bit 0) to 0 for a DCO output frequency of 16.78 MHz.
can be achieved with a 32.768 kHz reference is desired, clear the DRS bit (bit 0) to 0 and set
the DMX32 bit (bit 5) to 1. The resulting DCO output (MCGOUT) frequency with the new
multiplier of 608 will be 19.92 MHz.
can be achieved with a 32.768 kHz reference is desired, set the DRS bit (bit 0) to 1 and set the
DMX32 bit (bit 5) to 1. The resulting DCO output (MCGOUT) frequency with the new
multiplier of 1216 will be 39.85 MHz.
Using a 32.768 kHz Reference
Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external
modes when using a high frequency range (RANGE = 1) external reference
clock. The DIV32 bit is ignored in all other modes.
MC9S08DZ128 Series Data Sheet, Rev. 1
NOTE
Freescale Semiconductor
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