MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 6

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Signals and Connections
6
TRST
TDO
TDI
TCK
TMS
DMA_REQ
BIG_ENDIAN
ETMTRACESYNC
ETMTRACECLK
ETMPIPESTAT [2:0]
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
PS
Signal Name
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] are selected in ETM mode.
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
Line pulse or H sync
Shift clock
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
Table 2. i.MXL Signal Descriptions (Continued)
MC9328MXL Technical Data, Rev. 8
CMOS Sensor Interface
LCD Controller
JTAG
DMA
ETM
Function/Notes
Freescale Semiconductor