78Q2123/F Maxim Integrated Products, 78Q2123/F Datasheet
78Q2123/F
Specifications of 78Q2123/F
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78Q2123/F Summary of contents
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Simplifying System Integration DESCRIPTION The 78Q2123 and 78Q2133, MicroPHY smallest 10BASE-T/100BASE-TX Fast Ethernet transceivers in the market. They include integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse- shaper and a low-power ...
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Data Sheet 1 Functional Description .................................................................................................................. 5 1.1 General ................................................................................................................................... 5 1.1.1 Power Management .................................................................................................... 5 1.1.2 Analog Biasing and Supply Regulation ........................................................................ 5 1.1.3 Clock Selection............................................................................................................ 5 1.1.4 Transmit Clock Generation .......................................................................................... 5 1.1.5 Receive Signal Qualification ........................................................................................ ...
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DS_21x3_001 4 Electrical Specifications .............................................................................................................. 23 4.1 Absolute Maximum Ratings ................................................................................................... 23 4.2 Recommended Operating Conditions .................................................................................... 23 4.3 DC Characteristics ................................................................................................................ 23 4.4 Digital I/O Characteristics ...................................................................................................... 24 4.5 Digital Timing Characteristics ................................................................................................ 25 4.5.1 RST Characteristics................................................................................................... 25 4.5.2 ...
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Data Sheet Figures Figure 1: RST Pulse Duration ................................................................................................................ 25 Figure 2: Transmit Inputs to the 78Q2123/78Q2133 ............................................................................... 25 Figure 3: Receive Outputs from the 78Q2123/78Q2133 ......................................................................... 26 Figure 4: MDIO as an Input to the 78Q2123/78Q2133 ............................................................................ 26 ...
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DS_21x3_001 1 Functional Description 1.1 General 1.1.1 Power Management The 78Q2123 and 78Q2133 have three power saving modes: • Chip Power-Down • Receive Power Management • Transmit High Impedance Mode Chip power-down is activated by setting the PWRDN bit in ...
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Data Sheet 1.1.5 Receive Signal Qualification The integrated signal qualifier has separate squelch and unsquelch thresholds. It also includes a built-in timer to ensure fast and accurate signal detection and line noise rejection. Upon detection of two or more ...
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DS_21x3_001 The received MLT-3 signal is converted to 5 bit NRZ code groups and output from the RX_ER and RXD[3:0] pins, RX_ER being the MSB of the data output. The RX_DV and TX_EN pins are unused in PCS Bypass mode. ...
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Data Sheet 1.4 Auto-Negotiation The 78Q2123/78Q2133 support the auto-negotiation functions of Clause 28 of IEEE-802.3 for 10/100 Mbps operation over copper wiring. This function can be enabled via register settings. The auto-negotiation function defaults to ON and bit MR0.12 ...
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DS_21x3_001 1.5 Media Independent Interface 1.5.1 MII Transmit and Receive Operation The MII interface on the 78Q2123/78Q2133 provide independent transmit and receive paths for both 10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard. The ...
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Data Sheet 1.6 Additional Features 1.6.1 LED Indicators There are two LED pins that can be used to indicate various states of operation of the 78Q2123/78Q2133. The function of these pins is programmable via the MR23 register as shown ...
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DS_21x3_001 2 Pin Description 2.1 Legend Type Description A Analog Pin CIU TTL-level Input with Pull-up CIS TTL-level Input with Schmitt Trigger CO CMOS Output S Supply 2.2 MII (Media Independent Interface) Signal Pin Type Description TX_CLK 15 COZ TRANSMIT ...
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Data Sheet RXD[3:0] [5:8] COZ RECEIVE DATA: Received data is provided to the MAC via RXD[3:0]. These pins are tri-stated in isolate mode. RX_ER 13 COZ RECEIVE ERROR: RX_ER is asserted high when an error is detected during frame ...
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DS_21x3_001 2.7 LED Signals (Programmability Is Secondary Requirement) Signal Pin Type Description LED0 4 CO PROGRAMMABLE LED. Active low. Default status: LINK OK. Active to indicate link with far end PHY. LED1 3 CO PROGRAMMABLE LED. Active low. Default status: ...
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Data Sheet 3 Register Description The 78Q2123/78Q2133 implement 13 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and ...
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DS_21x3_001 3.1 MR0: Control Register Bit Symbol Type Default 0.15 RESET R/WC 0.14 LOOPBK R/W 0.13 SPEEDSL R/W 0.12 ANEGEN R/W 0.11 PWRDN R/W 0.10 ISO R/W 0.9 RANEG R/WC 0.8 DUPLEX R/W 0.7 COLT R/W 0.6:0 RSVD R Rev. ...
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Data Sheet 3.2 MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) ...
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DS_21x3_001 1.0 EXTD R 3.3 MR2: PHY Identifier Register 1 Bit Symbol Type 2.15:0 OUI [23:6] R 000Eh 3.4 MR3: PHY Identifier Register 2 Bit Symbol Type 3.15:10 OUI [5:0] R 3.9 3.3 3.5 MR4: Auto-Negotiation ...
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Data Sheet 4.5 A0 R/W 4.4:0 S4:0 R Note: Technology Ability Field: MR4.12:5 are the Technology Ability Field bits (A7:0). The default value of this field is dependent upon the MR1.15:11 register bits. This field can be overwritten by ...
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DS_21x3_001 16.14 INPOL R/W 16.13 RSVD R 16.12 TXHIM R/W 16.11 SQEI R/W 16.10 NL10 R/W 16.9 RSVD R 16.8 RSVD R 16.7 RSVD R 16.6 RSVD R 16.5 APOL R/W 16.4 RVSPOL R/W 16.3:2 RSVD R/W 16.1 PCSBP R/W ...
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Data Sheet 3.9 MR17: Interrupt Control/Status Register The Interrupt Control/Status Register provides the means for controlling and observing the events, which trigger an interrupt on the INTR pin. This register can also be used in a polling mode via ...
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DS_21x3_001 3.10 MR18: Diagnostic Register Bit Symbol Type 18.15:13 RSVD R 18.12 ANEGF RC 18.11 DPLX R 18.10 RATE R 18.9 RXSD R 18.8 RX_LOCK R 18.7:0 RSVD R 3.11 MR19: Transceiver Control Bit Symbol Type 19.15:14 TXO[1:0] R/W 19.13:0 ...
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Data Sheet 3.15 MR23: LED Configuration Register Bit Symbol Type 23.15:8 Reserved NA 23.7:4 LED1[3:0] R/W 23.3:0 LED0[3:0] R/W 3.16 MR24: MDI/MDIX Control Register Bit Symbol Type 24.15:8 Reserved R 24.7 PD_MODE R/W 24.6 AUTO_SW R/W 24.5 MDIX R/W ...
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DS_21x3_001 4 Electrical Specifications 4.1 Absolute Maximum Ratings Operation above maximum rating may permanently damage the device. Parameter DC Supply Voltage (Vcc) Storage Temperature Pin Voltage (except TXOP/N) Pin Voltage (TXOP/N only) Pin Current 4.2 Recommended Operating Conditions Unless otherwise ...
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Data Sheet 4.4 Digital I/O Characteristics Pins of type CI, CIU, CID, CIO Parameter Symbol Input Voltage Low Vil Input Voltage High Vih Input Current Iil, Iih Pull-up Resistance Rpu Input Capacitance Cin Pins of type CIS Parameter Symbol ...
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DS_21x3_001 4.5 Digital Timing Characteristics 4.5.1 RST Characteristics VCC Oscillator RST Parameter Symbol RST Pulse Assertion Treset 4.5.2 MII Transmit Interface Characteristics Symbol Setup Time: TX_CLK to TX TXD[3:0], TX_EN, TX_ER Hold Time: TX_CLK to TX TXD[3:0], TX_EN, TX_ER CKIN-to-TX_CLK ...
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Data Sheet 4.5.3 MII Receive Interface Characteristics Symbol Receive Output Delay: RX RX_CLK to RXD[3:0], RX_DV, RX_ER RX_CLK Duty-Cycle Figure 3: Receive Outputs from the 78Q2123/78Q2133 4.6 MDIO Interface Input Timing Characteristics Symbol Setup Time: MDC to MDIO MIO ...
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DS_21x3_001 4.6.1 MDIO Interface Output Timing Characteristics Symbol MDC to MDIO data delay MC2D MDIO output from high Z MCZ2D to driven after MDC MDIO output from driven MCD2Z to high Z after MDC Figure 5: MDIO as an Output ...
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Data Sheet 4.6.2 MDIO Interface Output Timing 28 Figure 6: MDIO Interface Output Timing DS_21x3_001 Rev. 1.6 ...
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DS_21x3_001 4.6.3 100BASE-TX System Timing System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3. Parameter TX_EN Sampled to first bit of “J” on MDI output First bit of “J” on MDI input ...
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Data Sheet 4.7 Analog Electrical Characteristics 4.7.1 100BASE-TX Transmitter Parameter Peak Output Amplitude Best-fit over 14 bit times; (|Vp+|, |Vp-|) 0.4 dB Transformer loss (see note below) Output Amplitude |Vp +| Symmetry |Vp -| Output Overshoot Percent of Vp+, ...
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DS_21x3_001 4.7.4 10BASE-T Transmitter The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. Parameter Peak Differential Output Signal (see note below) Harmonic ...
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Data Sheet R4 R5 VCC 100 100 R6 R7 100 100 VCC C5 0.1uF MDIO MDC RXD3 RXD2 R11 R10 RXD1 100 100 RXD0 RXDV RXCLK RXER TXER TXCLK TXEN TXD0 R12 R13 TXD1 100 100 TXD2 TXD3 COL ...
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DS_21x3_001 4.8 Isolation Transformers Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Name Turns Ratio Open-Circuit Inductance Leakage ...
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Data Sheet Figure 8: External XTLP Oscillator Characteristics 4.9.1 External XTLP Oscillator Characteristics Parameter Symbol XTLP Input Level XTLN Input Low Voltage XTLP Frequency f XTLP Period Tclkper XTLP Duty Cycle Rise / Fall Time Tr, Tf Absolute Jitter ...
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DS_21x3_001 5 Package Pin Designations (Top View) MDIO MDC LED1 LED0 RXD3 RXD2 RXD1 RXD0 Note: For information only, actual package outline will vary depending on package type. Rev. 1 TERIDIAN 4 78Q2123 5 78Q2133 6 7 ...
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Data Sheet 6 32-Pin QFN Mechanical Specifications Dimensions in mm TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 10: 32-Pin QFN Mechanical Specifications 36 / 0.85 NOM. 0.9MAX. 2.5 3.0 / 3.2 0.18 / 0.3 ...
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... Lead-Free 32-QFN, Industrial Temp 78Q2133, Lead-Free 32-QFN, Industrial Temp, Tape and Reel Rev. 1 Min Lead pitch See Note 1 3.93 mm Order Number 78Q2123/F 78Q2123R/F 78Q2133/F 78Q2133R/F 78Q2123/78Q2133 Data Sheet Typ Max 0.50 mm 0.28 mm 0.28 mm 0.69 mm 3.00 mm 3.78 mm Package Mark 78Q2123 xxxxxP7F ...
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Data Sheet Revision History Rev. # Date 1.0 9/15/2005 1.6 4/16/2010 Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian ...