78Q2123/F Maxim Integrated Products, 78Q2123/F Datasheet - Page 9

• Manufacturer Part Number: 78Q2123/F
• Description: TXRX 10/100 MDIX 3.3V COMM 32QFN
• Manufacturer: Maxim Integrated Products
• Type: 10/100 Fast Ethernetr

Specifications of 78Q2123/F

• Operating Supply Voltage: 3.3 V
• Supply Current: 88 mA
• Operating Temperature Range: 0 to + 70 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Operating Frequency: 25 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TX_ER signals from the MAC to the 78Q2123/78Q2133. TXD3-0 is captured on the rising edge of
TX_CLK when TX_EN is asserted. TX_ER is also captured on the rising edge of TX_CLK and is
asserted by the MAC to request that an error code group is to be transmitted. The assertion of TX_ER is
ignored when the 78Q2123/78Q2133 are operating in 10BASE-T mode.
The receive clock, RX_CLK, provides the timing reference to transfer RX_DV, RXD3-0, and RX_ER
signals from the 78Q2123/78Q2133 to the MAC. RX_DV transitions synchronously with respect to
RX_CLK and is asserted when the 78Q2123/78Q2133 are presenting valid data on RXD3-0. RX_ER is
asserted and is synchronous to RX_CLK when a code group violation has been detected in the current
receive packet.
REGAD fields. The default address for the 78Q2123/78Q2133 is 1. For a read operation, the MDIO port
becomes enabled as an output and the register data is loaded into a shift register for transmission. The
78Q2123/78Q2133 can work with a one-bit preamble rather than the 32 bits prescribed by IEEE-802.3.
This allows for faster programming of the registers. If a register does not exist at an address indicated by
the REGAD field or if the PHYAD field does not match the 78Q2123/78Q2133 PHYAD, a read of the
MDIO port will return all ones. For a write operation, the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been received. Writes to registers not supported by the
78Q2123/78Q2133 are ignored.
When the PHYAD field is all zeros, the Station Management Entity (STA) is requesting a broadcast data
transaction. All PHYs sharing the same Management Interface must respond to this broadcast request.
The 78Q2123/78Q2133 will respond to the broadcast data transaction.
DS_21x3_001
1.5
1.5.1 MII Transmit and Receive Operation
The MII interface on the 78Q2123/78Q2133 provide independent transmit and receive paths for both
10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard.
The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN, TXD3-0, and
1.5.2 Station Management Interface
The station management interface consists of circuitry which implements the serial protocol as described
in Clause 22.2.4.4 of IEEE-802.3. A 16-bit shift register receives serial data applied to the MDIO pin at
the rising-edge of the MDC clock signal. Once the preamble is received, the station management control
logic looks for the start-of-frame sequence and a read or write op-code, followed by the PHYAD and
Rev. 1.6
Media Independent Interface
78Q2123/78Q2133 Data Sheet
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