78P2351R-IMR/F Maxim Integrated Products, 78P2351R-IMR/F Datasheet - Page 10

• Manufacturer Part Number: 78P2351R-IMR/F
• Description: IC LIU NRZ-CMI CONV 155M 56-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351R-IMR/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER DESCRIPTION
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and
the read/write operation will be ignored.
ADDRESS 1-0: MODE CONTROL REGISTER
Page: 10 of 31
BIT
1:0
7
6
5
4
3
2
SMOD[1]
SMOD[0]
NAME
PDRX
PDTX
MON
--
--
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
DFLT
01
X
X
0
0
0
0
(continued)
DESCRIPTION
Transmitter Power-Down:
Receiver Power-Down:
Reserved.
Serial Mode Interface Selection:
SMOD[1] SMOD[0]
Note: Default values depend on the CKMODE pin setting upon reset or
power up.
Receive Monitor Mode Enable:
Reserved.

0
1
0
1
2006 Teridian Semiconductor Corporation
0 : Normal Operation
1 : Power-Down. CMI Transmit output is tri-stated.
0 : Normal Operation
1 : Power-Down
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization.
0
0
1
1
Reserved
Synchronous data is passed through the CDR and
then through the FIFO.
Plesiochronous data is passed through the CDR to
recover a clock, but the FIFO is bypassed because
the data is not synchronous with the reference clock.
Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit DLL
and FIFO.
NRZ to CMI Converter
Serial 155M
78P2351R
Rev. 2.1