78P2351R-IMR/F Maxim Integrated Products, 78P2351R-IMR/F Datasheet - Page 5

• Manufacturer Part Number: 78P2351R-IMR/F
• Description: IC LIU NRZ-CMI CONV 155M 56-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351R-IMR/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TRANSMITTER OPERATION
The transmitter section generates an adjustable
ITU-T
transmission through a wideband transformer onto
75Ω coaxial cable. Differential NRZ data is input to
the 78P2351R on the SIDP/N pins at LVPECL levels
and passed to a low jitter clock and data recovery
circuit.
provided to decouple the on chip and off chip clocks.
The NRZ data is encoded using CMI line coding to
ensure an adequate number of transitions.
Each of the transmit timing modes can be configured
in HW mode or SW mode as shown in the table
below.
Tx Mode
Reserved
Synchronous
(FIFO enabled)
Plesiochronous
Loop-timing
Plesiochronous Mode
Plesiochronous
condition where a synchronous reference clock is
not available.
recover the transmit clock from the plesiochronous
data and bypass the internal FIFO and re-timing
block. This mode is commonly used for mezzanine
cards, modules, and any application where the
reference clock can’t always be synchronous to the
transmit source clock/data
Page: 5 of 31
Framer/
Mapper
System
Clock
G.703
Figure 1: Plesiochronous Mode
An optional clock decoupling FIFO is
NRZ
NRZ
In this mode, the 78P2351R will
compliant
mode
HW Control
SIDP/N
SODP/N
Floating
CKMODE
High
Low
n/a
CKREFP
represents
78P2351R
TDK
analog
XO
CMIP/N
RXP/N
SW Control

SMOD[1:0]
a
signal
2006 Teridian Semiconductor Corporation
CMI
CMI
0 0
1 0
0 1
1 1
common
XFMR
XFMR
for
Coax
Coax
Synchronous Mode
When the NRZ transmit data is source synchronous
with the reference clock applied at CKREFP/N as
shown in Figure 2, the 78P2351R can be optionally
used in synchronous mode or re-timing mode. In
this mode, the 78P2351R will recover the clock from
the NRZ data input and re-time the data in an
integrated +/- 4-bit FIFO.
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
specified limits, the FIFO will over or under flow, and
the FERR register signal will be asserted.
signal can be used to trigger an interrupt.
interrupt event is automatically cleared when a FIFO
Reset (FRST) pulse is applied, and the FIFO is re-
centered.
Clock Synthesizer
The transmit clock synthesizer is a low-jitter PLL that
generates a 311.04 MHz clock for the CMI encoder.
A synthesized 155.52 MHz reference clock is also
used in both the receive and transmit sides for clock
and data recovery.
Framer/
Mapper
System Reference Clock
Notes:
1) External remote loopbacks (i.e. loopback
2) During IC power-up or transmit power-up,
within
synchronous
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2351R is configured for loop-
timing operation.
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow.
manually reset using FRST anytime the
transmitter is powered-up.
Figure 2: Synchronous
NRZ
NRZ
framer)
If the clock wander exceeds the
SIDP/N
SODP/N
As such, the FIFO should be
NRZ to CMI Converter
operation
CKREFP/N
78P2351R
are
TDK
not
(FIFO
CMIP/N
RXP/N
Serial 155M
78P2351R
possible
CMI
CMI
enabled)
XFMR
XFMR
Rev. 2.1
This
This
Coax
Coax
in