78P2351-IGT/F Maxim Integrated Products, 78P2351-IGT/F Datasheet - Page 14

• Manufacturer Part Number: 78P2351-IGT/F
• Description: LINE INTERFACE UNIT 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351-IGT/F

• Number Of Channels Per Chip: 1
• Propagation Delay Time: 10 ns
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER DESCRIPTION
ADDRESS 1-1: SIGNAL CONTROL REGISTER
Page: 14 of 42
BIT
7
6
5
4
3
2
1
0
RCMIINV
TCMIINV
LOLOR
RCLKP
TCLKP
NAME
RLBK
FRST
LLBK
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
DFLT
0
0
0
0
0
0
0
0
(continued)
DESCRIPTION
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIP/N.
For debug use only.
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXP/N. For
debug use only.
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
NOTE: For reliable operation of the Rx LOL detection circuitry, one must
manually reset the LOL counter by toggling this bit upon power-up or
initialization.
Analog Loopback Selection:
RLBK
Receive Clock Inversion Select:
This bit will invert the receive output clock.
Transmit Clock Inversion Select:
This bit will invert the transmit input system clock.
FIFO Reset:
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.

0
1
0
2006 Teridian Semiconductor Corporation
0: Normal
1: Invert
0: Normal
1: Invert
0: Normal
1: Forces LOS and LOL outputs to be low and resets counters
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
0: Normal operation
1: Reset FIFO pointers to default locations.
NOTES: Transmit monitor port will also be affected by FRST, FIFO
resets not required for Plesiochronous Serial Mode
LLBK
0
0
1
Normal operation
Remote Loopback Enable: Recovered receive data
is looped back to the transmit driver
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
OC-3/ STM1-E/ E4 LIU
Single Channel
78P2351
Rev. 2.4