ST16C2550IQ48-F Exar Corporation, ST16C2550IQ48-F Datasheet - Page 14

• Manufacturer Part Number: ST16C2550IQ48-F
• Description: IC DUART FIFO 16B 48TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 485r

Specifications of ST16C2550IQ48-F

• Number Of Channels: 2, DUART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 4 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1256

ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
2.10.1
Receive Holding Register (RHR) - Read-Only
F
IGURE
Receive Data
Byte and Errors
16 bytes by 11-bit
F
IGURE
16X Clock
10. R
wide FIFO
16X Clock
and Errors
9. R
Data Byte
ECEIVER
Receive
ECEIVER
Receive Data Shift
O
Register (RSR)
PERATION IN
O
LSR bits
RX FIFO
Tags in
Error
PERATION IN NON
4:2
RHR
Receive Data Shift
Register (RSR)
Holding Register
Receive Data
FIFO M
Validation
Data Bit
(RHR)
14
ODE
-FIFO M
Validation
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
FIFO is Enabled by FCR bit-0=1
Data Bit
ODE
RHR Interrupt (ISR bit-2)
Receive Data Characters
Receive Data Characters
RXFIFO1
RXFIFO1
REV. 4.4.1