ST16C554CQ64-F Exar Corporation, ST16C554CQ64-F Datasheet - Page 14
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ST16C554CQ64-F
Manufacturer Part Number
ST16C554CQ64-F
Description
IC UART FIFO 16B QUAD 64LQFP
Manufacturer
Exar Corporation
Type
Quad UART with 16-byte FIFOsr
Datasheet
1.ST16C554DCJ68-F.pdf
(39 pages)
Specifications of ST16C554CQ64-F
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
16 Byte
Protocol
RS232
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
1.5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
6 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V, 5 V
No. Of Channels
4
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1264
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST16C554CQ64-F
Manufacturer:
EXAR
Quantity:
10
Company:
Part Number:
ST16C554CQ64-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
ST16C554CQ64-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
The 554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 10
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
F
2.11
IGURE
10. I
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
NTERNAL
L
OOP
B
ACK IN
Transmit Shift Register
Receive Shift Register
C
(THR/FIFO)
(RHR/FIFO)
HANNEL
A
RTS#
CTS#
DTR#
DSR#
CD#
AND
RI#
MCR bit-4=1
B
14
VCC
VCC
OP1#
OP2#
VCC
TX A-D
RX A-D
RTS# A-D
CTS# A-D
DTR# A-D
DSR# A-D
RI# A-D
CD# A-D
REV. 4.0.1