ST16C654IJ68-F Exar Corporation, ST16C654IJ68-F Datasheet - Page 50

• Manufacturer Part Number: ST16C654IJ68-F
• Description: IC UART FIFO 64B QUAD 68PLCC
• Manufacturer: Exar Corporation

Specifications of ST16C654IJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1272

ST16C654/654D
REV. 5.0.2
GENERAL DESCRIPTION .................................................................................................1
PIN DESCRIPTIONS .........................................................................................................4
1.0 PRODUCT DESCRIPTION .....................................................................................................................8
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................9
3.0 UART INTERNAL REGISTERS ...........................................................................................................22
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................24
F
A
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE .............................................................................................................................................. 9
2.2 DEVICE RESET .............................................................................................................................................. 10
2.3 CHANNEL SELECTION .................................................................................................................................. 10
2.4 CHANNELS A-D INTERNAL REGISTERS .................................................................................................... 11
2.5 INT OUPUTS FOR CHANNELS A-D .............................................................................................................. 11
2.6 DMA MODE ..................................................................................................................................................... 11
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 12
2.8 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 12
2.9 TRANSMITTER ............................................................................................................................................... 13
2.10 RECEIVER .................................................................................................................................................... 15
2.11 AUTO RTS HARDWARE FLOW CONTROL ................................................................................................ 16
2.12
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18
2.14
2.15 INFRARED MODE ........................................................................................................................................ 19
2.16
2.17
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 24
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
F
F
F
F
T
T
T
T
T
F
F
T
F
F
F
F
F
T
T
F
F
T
T
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
ABLE
ABLE
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ......................................................................................... 13
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 14
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 14
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 15
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 25
AUTO CTS FLOW CONTROL ..................................................................................................................... 16
SPECIAL CHARACTER DETECT ............................................................................................................... 18
SLEEP MODE WITH AUTO WAKE-UP ....................................................................................................... 20
INTERNAL LOOPBACK .............................................................................................................................. 20
1: C
2: C
3: INT P
4: INT P
5: TXRDY#
6: T
7: A
8: A
9:
10:
1. ST16C654 B
2. P
3. P
4. ST16C654/654D T
5. T
6. B
7. T
8. T
9. R
10. R
11. A
12. I
13. I
.....................................................................................................................................................1
YPICAL DATA RATES WITH A
UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 22
UTO
UTO
HANNEL
HANNEL
YPICAL OSCILLATOR CONNECTIONS
RANSMITTER
RANSMITTER
INTERNAL REGISTERS DESCRIPTION. S
IN
IN
AUD
ECEIVER
NFRARED
NTERNAL
................................................................................................................................................1
UTO
ECEIVER
O
O
INS
IN
RTS/CTS F
X
UT
UT
R
ON
O
RTS
ATE
A-D S
A-D S
O
AND
A
A
PERATION FOR
/X
PERATION FOR
O
SSIGNMENT
SSIGNMENT
L
OFF
T
O
G
PERATION IN NON
OOP
AND
RANSMIT
LOCK
RXRDY# O
PERATION IN
ENERATOR AND
O
O
.................................................................................................................................3
ELECT IN
ELECT IN
PERATION IN NON
PERATION IN
(S
LOW
CTS F
B
OFTWARE
ACK IN
D
YPICAL
IAGRAM
C
D
F
F
OR
OR
ONTROL
ATA
R
LOW
16 M
68 M
T
UTPUTS IN
ECEIVER FOR
C
FIFO
RANSMITTER FOR
I
100-
PLCC P
NTEL
14.7456 MH
) F
HANNEL
E
........................................................................................................................................... 1
FIFO
C
-FIFO M
ODE
ODE
P
NCODING AND
TABLE OF CONTENTS
LOW
ONTROL
RESCALER
PIN
.................................................................................................................................... 17
/M
AND
-FIFO M
................................................................................................................................. 10
................................................................................................................................. 10
OTOROLA
AND
............................................................................................................................... 12
C
QFP P
ACKAGES
FIFO
A
A
ONTROL
ODE
AND
UTO
C
O
F
Z CRYSTAL OR EXTERNAL CLOCK
HANNELS
LOW
PERATION
..................................................................................................................... 13
ODE
AND
.................................................................................................................... 15
ACKAGES
B ................................................................................................................ 21
RTS F
R
C
D
I
ECEIVE
............................................................................................................... 18
HANNELS
C
N
ATA
.............................................................................................................. 14
DMA M
HADED BITS ARE ENABLED WHEN
ONTROL
16
LOW
A-D ................................................................................................. 11
B
....................................................................................................... 17
AND
US
I
I
D
N
ODE FOR
ATA
C
16
A-D ......................................................................................... 11
I
68 M
M
NTERCONNECTIONS
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
ONTROL
ODE
AND
D
ECODING
ODE AND
..................................................................................... 14
68 M
C
M
HANNELS
ODE
ODE
.......................................................................... 19
LQFP P
....................................................................... 16
........................................................................ 2
...................................................................... 13
A-D ........................................................... 12
................................................................... 9
ACKAGES
EFR B
IT
-4=1....................................... 23
................................................ 3
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