XR17D154IV-F Exar Corporation, XR17D154IV-F Datasheet - Page 29

• Manufacturer Part Number: XR17D154IV-F
• Description: IC UART PCI BUS QUAD 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D154IV-F

• Number Of Channels: 4, QUART
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1290

xr
REV. 1.2.2
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. While transmitting, the RTS# or DTR# signal is HIGH. The RTS# or DTR# signal changes from HIGH to
LOW after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been
transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay
optimizes the time needed for the last transmission to reach the farthest station on a long cable network before
switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal
degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty.
F
F
5.2.3
5.2.4
IGURE
IGURE
12. T
13. T
(8XMODE Register)
Auto Software Flow Control
(Xoff1/2 and Xon1/2 Reg.
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(8XMODE
16X or 8X
16X or 8X Clock
Transmitter Operation in FIFO mode
Auto RS485 Operation
Register)
Clock
RANSMITTER
RANSMIITTER
Data
Byte
O
O
Data Byte
Transmit
PERATION IN NON
PERATION IN
Transmit Shift Register (TSR)
Transmit
Register
Holding
(THR)
FIFO
Transmit Data Shift Register
-FIFO M
AND
F
(64-Byte)
Transmit
LOW
ODE
FIFO
(TSR)
29
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
ODE
THR Interrupt (ISR bit-1) falls
when becomes empty. FIFO
below Programmed Trigger
is Enabled by FCR bit-0=1
Level (TXTRG) and then
M
S
B
TXNOFIFO1
L
S
B
TXFIFO1
XR17D154