71M6513-IGTR/F Maxim Integrated Products, 71M6513-IGTR/F Datasheet - Page 23

• Manufacturer Part Number: 71M6513-IGTR/F
• Description: IC ENERGY METER 3PH 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6513-IGTR/F

• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Supply Current (max): 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
WDI
INTBITS
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated
op-codes is contained in the 651X Software User’s Guide (SUG).
UART
The 71M6513 includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second
UART (UART1) is connected to the optical port, as described in the optical port description.
The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s
((with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied
at RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6513 has several UART-related registers for the control and buffering of serial data.. A single SFR register serves as
both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1). When written by
the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the receive buffer. Writing data to the
transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive
buffer. Both UARTs can simultaneously transmit and receive data.
A Maxim Integrated Products Brand
INT0…INT6
Alternative
Name
Address
0xE8
0xF8
SFR
© 2005-2011 Teridian Semiconductor Corporation
Table 11: Special Function Registers
R/W
R/W
R/W
R/W
W
W
R
R
Description
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
Only byte operations on the whole WDI register should be used
when writing. The byte must have all bits set except the bits that are
to be cleared.
The multi-purpose register WDI contains the following bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by hardware
and must be cleared by the interrupt handler
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by hardware and
must be cleared by the interrupt handler
Bit 7 (WD_RST): WD Timer Reset:
The WDT is reset when a 1 is written to this bit.
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use
1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
3-Phase Energy Meter IC
71M6513/71M6513H
DATA SHEET
SEPTEMBER 2011
Page: 23 of 104