XRP7714ILB-F Exar Corporation, XRP7714ILB-F Datasheet - Page 14

• Manufacturer Part Number: XRP7714ILB-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Type: Step-Down (Buck)r

Specifications of XRP7714ILB-F

• Number Of Outputs: 4
• Package / Case: 40-WFQFN Exposed Pad
• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Voltage - Output: 0.9 ~ 5.1 V
• Frequency - Switching: 300kHz ~ 1.5MHz
• Voltage - Input: 4.75 ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Switching Frequency: 300 KHz
• Operating Supply Voltage: 4.75 V to 25 V
• Supply Current: 28 mA to 50 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Output Voltage: 0.9 V to 5.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1350 - EVAL BAORD FOR XRP77141016-1344 - IN-SOCKET PROG BRD VIA USB/GUI
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1351

For enabling a specific channel, there are several ways that this can be achieved. The chip can be
configured to enable a channel at start-up as the default configuration residing in the non-volatile
configuration memory of the IC. The channels can also be enabled using GPIO pins and/or an I
Bus serial command. The registers that control the channel enable functions are the
SET_EN_CONFIG and SET_CH_EN_I2C.
I
The XRP7714 integrates Internal Gate Drivers for all 4 PWM channels. These drivers are optimized
to drive both high-side and low side N-MOSFETs for synchronous operations. Both high side and
low side drivers have the capability of driving 1nF load with 30ns rise and fall time. The drivers
have built-in non-overlapping circuitry to prevent simultaneous conduction of the two MOSFETs.
The built-in non-overlapping feature is disabled when the programmable dead time is selected.
P
The programmable dead time feature provides customers the flexibility to optimize the system
performance over PWM switching frequency, efficiency and component selections.
There are three registers to control the dead time. The programmable dead time feature is enabled
in the SET_CONTROL_BIT_REG register. If disabled, the built-in dead time control inside the driver
will take over.
The dead time between the turn off of the low side MOSFET and the turn on of high side MOSFET is
controlled by the SET_DT_RISE_CHx. On the other hand, the dead time between the turn off of
high side MOSFET and the turn on of the low side MOSFET is controlled by SET_DT_FALL_CHx. The
actual LSB of the registers is variable depending on the switching frequency.
F
While the chip is operating there are four different types of fault handling:
There are two locations where the under voltage can be sensed: VIN1 and VIN2. The
SET_UVLO_WARN_VINx register that sets the under voltage warning set point condition at 100mV
increments. When the warning threshold is reached, the Host is informed via a GPIO or by reading
the READ_WARN_FLAG register.
The SET_UVLO_TARG_VINx register that controls the under voltage fault set point condition at
100mV increments. This fault condition will be indicated in the READ_FAULT_WARN register.
© 2010 Exar Corporation
NTERNAL
AULT
Under Voltage Lockout (UVLO)
ROGRAMMABLE
•
•
•
•
H
Under Voltage Lockout (UVLO) monitors the input voltage to the chip, and the chip will
shutdown all channels if the voltage drops to critical levels.
Over Temperature Protection (OTP) monitors the temperature of the chip, and the chip
will shutdown all channels if the temperature rises to critical levels.
Over Voltage Protection (OVP) monitors the voltage of channel and will shutdown the
channel if it surpasses its voltage threshold.
Over Current Protection (OCP) monitors the current of a channel, and will shutdown the
channel if it surpasses its current threshold. The channel will be automatically restarted
after a 200ms delay.
ANDLING
G
ATE
D
D
RIVERS
EAD
T
IME
Q
Q
u
u
a
a
d
d
C
C
h
h
a
a
14/27
n
n
n
n
e
e
l
l
D
D
i
i
g
g
1
i
i
t
t
256
a
a
l
l
P
P
W
W
M
M
S
S
t
t
e
e
p
p
D
D
o
o
w
w
n
n
X
X
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.3
t
t
7
7
r
r
o
7
o
7
l
l
1
1
l
l
e
e
2
4
4
C
r
r