STEVAL-CCA018V1 STMicroelectronics, STEVAL-CCA018V1 Datasheet - Page 5

• Manufacturer Part Number: STEVAL-CCA018V1
• Description: EVAL BOARD A/D TS4657
• Manufacturer: STMicroelectronics
• Type: Other Power Managementr

Specifications of STEVAL-CCA018V1

• Design Resources: STEVAL-CCA018V1 BOM STEVAL-CCA018V1 Schematic
• Featured Product: STM32 Cortex-M3 Companion Products
• Main Purpose: Audio, Audio Processing
• Embedded: No
• Utilized Ic / Part: TS4657
• Primary Attributes: I²S, Right- or Left- Justified
• Secondary Attributes: 3 V ~ 5.5 V Supply
• Interface Type: I2C
• Operating Supply Voltage: 3 V to 5.5 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: TS4657
• Other names: 497-10735

AN3001
3
3.1
Table 3.
3.2
FORMAT2
0
0
1
1
Configuring the demonstration board
Serial data input configuration
The TS4657 receives serial digital audio data through a 3-wire interface. SDAT is the serial
audio data input. The data is entered MSB first and is a two’s complement. The data can be
I
FORMAT2 as detailed in
The level on both of these pins should be fixed before waking-up the chip.
Digital audio data formats supported by the TS4657
Sample rate capability
Three external clock signals are applied to the TS4657. The MCLK is the external master
clock applied by the audio data processor. The LRCLK is the channel frequency, also called
LEFT/RIGHT clock, at which the digital words for each channel are input to the device. The
LRCLK clock is the sample rate of the audio data. The ratio MCLK/LRCLK must be an
integer, as shown in
The BCLK is the bit clock and represents the clock at which the audio data is serially shifted
into the audio port. BCLK is linked to LRCLK. The minimum required BCLK frequency is
twice the audio sample rate multiplied by the number of bits in each audio word. Refer to
Table 3
signals.
Table 4.
2
S, right- or left-justified. The data format is chosen with the control pins FORMAT1 and
FORMAT1
0
1
0
1
for the BCLK/LRCLK ratio. MCLK, LRCLK and BCLK must be synchronous clock
Audio data sampling rates
LRCLK (kHz)
Right-justified, 16-bit data
Data valid on rising edge of BCLK
Right-justified, 24-bit data
Data valid on rising edge of BCLK
Left-Justified, 16-bit up to 24-bit data
Data valid on rising edge of BCLK
I²S, 16-bit up to 24-bit data
Data valid on rising edge of BCLK
44.1
32
48
Table
Table
Data Format
4.
Doc ID 15911 Rev 1
3.
Configuring the demonstration board
2 x number of bits of data
2 x number of bits of data
MCLK (MHz)
11.2896
12.288
8.192
BCLK/LRCLK ratio
256x
Min
32
48
Max
256
256
256
256
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