73S8009C-DB Maxim Integrated Products, 73S8009C-DB Datasheet - Page 14

• Manufacturer Part Number: 73S8009C-DB
• Description: BOARD DEMO 73S8009C 32-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S8009C-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

73S8009C Demo Board User Manual
5 73S8009C Demo Board Schematics, PCB Layouts and Bill of Materials
5.1
14
Note: VPCIN
must be
between 2.7
and 6.5V
J1 and J3 are placed on the bottom.
are placed on the top side.
J1 and J3 must be aligned with J8 and J9 on the
1121 evaluation board (E1121T8) respectivly in
order for this board to be stacked on it.
J1 must be aligned with J2 and J3 must be
aligned with J4 in order for this daughter
board to be stacked on another.
CMDVCC5
CMDVCC3
OFF_ACK
OFF_REQ
Schematics
VPCIN
VPCIN
RSTIN
+3.3V
SCLK
SSM_110_L_SV
TSM_110_01_L_SV
SSM_110_L_SV
TSM_110_01_L_SV
USR7
SIO
SC4
SC8
OFF
GND
GND
GND
RDY
GND
CS
J1
10
J2
10
J3
10
J4
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VPCIN
3.3V
J2 and J4
CARD DETECT
POLARITY
SELECT
Figure 4: 73S8009C Electrical Schematic
CS
Disable
Note: JP4 pins 1
and 2 must not be
connected with JP2
pins 1 and 2 at the
same time.
Note: JP4 pins 1
and 2 should only
be connected when
3.3V is not sourced
from the mating
board (if
applicable)
JP7
1
2
JP5
JP6
IOUC
AUX1UC
AUX2UC
CMDVCC%
CMDVCC%
CMDVCC%
CMDVCC%
CMDVCC%
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
CMDVCC#
RSTIN
CLKIN
RDY
OFF_ACK
OFF_REQ
CS
1
2
3
1
2
3
PRES
PRES
VDD
GND
JP4
1
2
0.1uF
U1
1
2
3
4
5
6
7
8
C3
73S8009C
3.3V
VDD
IOUC
AUX1UC
AUX2UC
CMDVCC5
CMDVCC3
RSTIN
CLKIN
RDY
R10
Ru
DNI
R13
Rd
DNI
PRES
PRES
3.3V
3.3V
VDD
L1
JP2
ON/OFF
C1
C2
VBUS
AUX1
AUX2
CLK
GND
VCC
RST
VPCIN
IO
C4
4.7uF
1
VPC
SELECT
10uF
I/O
C8
24
23
22
21
20
19
18
17
0.1uF
TP1
TP9
TP4
TP6
1
R7 0
1
2
1
2
J5
IO
AUX1
AUX2
VCC
RST
Smart Card Connector
1
TP2
C1, C2, C3 and L1 must be placed
within 5mm of the U1 pins and
connected by thick track (wider
than 0.5mm)
JP3
R8
Ru
DNI
R11
Rd
DNI
TP3
TP5
TP7
TP8
J6
1
2
1
2
1
2
1
2
1
UM_8009C_059
S1 SW
R9
Ru
DNI
R12
Rd
DNI
SIM/SAM Connector
VCC
RST
CLK
C4
2
R8 to R13 and C36 to be
placed within 1cm of
J7.
TP3 to TP8, C9, C11 and
C12 are to be placed
very close to the pads
of J5
Rev. 1.3
C12
30pF
C9
30pF
C11
0.47uF