73M1903C-EVM Maxim Integrated Products, 73M1903C-EVM Datasheet - Page 10

• Manufacturer Part Number: 73M1903C-EVM
• Description: BOARD DEMO 73M1903C WORLDWIDE
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903C-EVM

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -

73M1903C Evaluation Board User Manual
At this point, the 73M1903C is guaranteed to be in the software controlled control frame mode. All the
MAFE serial data will be data only unless the host requests a control frame by setting the LSB of the TX
data to a one by setting bit 0 of data frame. The following frame will then be a control frame.
B. Control Frame Generation
Example 1: Using the Software Controlled Control Frame:
Example 2: Using the Automatic Control Frame (Hardware Controlled Control Frame)
10
static const U16 init_afe_config[] =
{
};
note: CTRL_FRAME = 0x0001
static const U16 init_afe_config[] =
FRAMES
{
CTRL2|0x00, CTRL2|0x00,
CTRL_FRAME, CTRL13|0x00,
CTRL_FRAME, CTRL1|ENFE,
CTRL_FRAME, CTRL2|0x00,
CTRL_FRAME, GPIO|0x00,
CTRL_FRAME, GDIR|0xD0,
CTRL_FRAME, GIE|0x00,
CTRL_FRAME, GIP|0x00,
CTRL_FRAME, BGTRIM|0x00,
CTRL_FRAME, TEST|0x00,
CTRL_FRAME, CTRL08|AFE_CTRL08,
CTRL_FRAME, CTRL09|AFE_CTRL09,
CTRL_FRAME, CTRL10|AFE_CTRL10,
CTRL_FRAME, CTRL11|AFE_CTRL11,
CTRL_FRAME, CTRL12H|AFE_CTRL12H,
CTRL_FRAME, CTRL12L|AFE_CTRL12L,
CTRL_FRAME, RWB|GPIO,
CTRL_FRAME, RWB|GPIO,
CTRL_FRAME, CTRL13|AFE_CTRL13
CTRL2|0x00, CTRL2|0x00,
CTRL_FRAME, CTRL13|0x00,
CTRL_FRAME, CTRL1|ENFE|HC,
0x0000, GPIO|0x00,
0x0000, GDIR|0xD0,
2. Reset the HC bit (Register 0x01 bit 0) in next frame sequence.
 Software Controlled Control Frame

1. Mask TXD Bit 0 as 1 to request a subsequent control frame.
2. Write or read the 73M1903C register using the MAFE control data format.
3. Make sure to Mask TXD bit 0 as 0 if the control frame is not needed.
1. Mask TXD Bit 0 as 1 to request a subsequent control frame.
2. Set the HC bit (Register 0x01 bit 0) using the MAFE control data format in the next frame.
From this point on, there will be alternating data and control frames. Make sure not to miss this
sequence. This is needed to initialize the HC mode.
Hardware Controlled Control Frame
// MUST HAVE Data(LSB=1), Control, Data(LSB=1), Control,.. FRAMES
// Force to Software controlled control frame
// Force to Xtal clock
// Enable Analog
//
//
// GPIO 7,6,4=in 5,3,2,1,0=output
// Timing chain set up
// Delay for 2 sample cycle time to
// let PLL settle before Lockdet
// MUST HAVE Dummy Data, Control, Dummy Data, Control,..
// Force to Software controlled control frame
// Force to Xtal clock
// Enable Analog
// Forces DATA to be 0x0000
// GPIO 7,6,4=in 5,3,2,1,0=output
UM_1903C_030
Rev. 2.0