78P2352-DB/CMI Maxim Integrated Products, 78P2352-DB/CMI Datasheet - Page 3

• Manufacturer Part Number: 78P2352-DB/CMI
• Description: BOARD DEMO 78P2352 COAX CABLE
• Manufacturer: Maxim Integrated Products

Specifications of 78P2352-DB/CMI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78P2352-DB Demo Board Manual
DEMO BOARD DESCRIPTION
CONFIGURING BIT RATE
The D2352T8C can be configured for either E4 or
STS3/STM1 rates by
A corresponding reference clock input is required for
operation. The compatible reference clocks for each
rate are as follows:
STS3 /STM1
S1
frequency based on the selected bit rate.
The 78P2352-DB provides on-board 17.408MHz
and 19.44MHz crystal oscillators as well as an SMA
connector for use of external reference clock
sources. Headers JP6 and JP7 allow easy selection
of the reference clock source.
LINE INTERFACE
The 78P2352-DB is pre-configured and shipped to
allow easy evaluation of the CMI encoded, coaxial
line interface.
Footprints for optics modules, however, are provided
for evaluating the optical line interface of the
78P2352. For more information on configuring the
D2352T8C board in optical (NRZ) mode, please
contact TERIDIAN’s applications support group.
CKSL
Float
Rate
NOTE:
other
Plesiochronous mode, an external reference
clock source must be provided at the SMA input
labeled CKREF and must be synchronous to the
transmit data (and timing) source.
(pin 7) is used to configure the reference clock
High
Low
E4
than
If using any system/timing interface
19.44MHz, 77.76MHz, 155.52 MHz
139.264 MHz, 155.52 MHz
17.408MHz, 139.264 MHz
SW1
the
17.408MHz, 19.44MHz
Reference Clock
Reference Clock
(pin 4).
77.76MHz
recommended
Serial
3
TRANSMIT SIGNAL PATH
The transmitter’s coaxial connectors are connected
to the LIU transmitter pins (CMxP, CMxN) through a
1:1CT (center-tapped) transformer. The transformer
center tap is tied to Vcc to bias the transmitter
drivers. The signal path is differentially terminated
with a 75Ω resistor on the LIU side of the
transformer. The termination resistor, in combination
with the characteristic impedance of the transformer
and the line impedance create the required pulse
shaping impedance for the LIU’s driver.
The user may configure serial or parallel interface by
changing
Plesiochronous mode is recommended to eliminate
the need for a synchronous timing relationship
between the transmit clock/data and the reference
clock.
When the parallel (system) interface is chosen,
the 48-pin box connector U2 can be used to
connect other digital control boards. By default
the LIU expects transmit data to clock in on the
rising clock edge so the transmitter source (i.e
framer) should clock out transmit data on the
clock’s falling edge. If using this interface, the
user must ensure the reference clock is
synchronous with the transmit clock/data source.
SMA connectors support the option for a serial
(system) interface. Each channel provides four
SMA connectors, two for the differential clock
(SIxCKP/N)
differential data signal (SIxDP/N). These inputs
accept LVPECL differential signals, which are
AC-coupled and differentially terminated with
100Ω at the LIU. If using any serial timing mode
other than Plesiochronous mode, the user must
ensure the reference clock is synchronous with
the transmit clock/data source.
SW1
and
(pin
two
3),
for
although
the
respective
Serial