78P2352-DB/CMI Maxim Integrated Products, 78P2352-DB/CMI Datasheet - Page 4

• Manufacturer Part Number: 78P2352-DB/CMI
• Description: BOARD DEMO 78P2352 COAX CABLE
• Manufacturer: Maxim Integrated Products

Specifications of 78P2352-DB/CMI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78P2352-DB Demo Board Manual
RECEIVE SIGNAL PATH
The line side (coax) receiver interface has the same
architecture as the transmit interface, except the
transformer winding’s center tap is left open. The
received signal is internally equalized for dispersive
cable attenuation and decoded in the CMI to NRZ
decoder.
The user may configure serial or parallel interface by
changing
Plesiochronous mode is recommended.
SUPPLEMENTAL SURGE PROTECTION
Optional surge protection circuitry is included on the
coax line side to ensure proper operation of the
device during the presence of differential voltage
surges, as called for by ITU-T, Bellcore, and IEC
specifications.
additional protection against ESD and power supply
transients at the power supply banana jacks.
Consult the application note for more information on
supplemental
interfaces.
LOOPBACK OPERATION
S1 (pins 2 and 3) also provides controls for
configuring the internal loopback modes.
DIFFERENTIAL TEST POINTS
The following test points are provided to facilitate
test and measurement.
If selecting the parallel interface, data to the
system (i.e. framer) passes through the 48-pin
box connector. The receive data is clocked out
at the falling edge of the receive clock. This is
the default state of the LIU.
SMA connectors support the option for a serial
(system) interface.
interface provides four SMA connectors, two for
the differential clock (SOxCKP/N) and two for
the
(SOxDP/N). These outputs provide LVPECL
differential signals, which are AC-coupled to the
system at the SMA connectors.
When the pin is pulled low, the chip is in the
normal mode.
When the pin is pulled high, the receiver uses
the transmitter output signal as its input, known
as local (analog) loopback.
When the pin is floating, the received signal is
looped back to the transmitter, known as remote
(digital) loopback.
respective
SW1
surge
Protection
(pin
differential
protection
Each channel’s serial
3),
diode
although
for
U3
data
electrical
provides
signal
Serial
4
Test Point
PDT1
PDT2
PDT3
PDT4
PDT5
PDT6
PDT7
PDT8
PDT9
PDT10
PDT13
PDT16
PDT14
PDT17
PDT15
PDT17
STATUS PINS
The 78P2352 provides both open drain and CMOS
versions for the status pins. On the demo board,
resistor population options are available to evaluate
different version of chips.
populated by open drain chips.
Open drain:
LOS1: R7 -- 0Ω, R96 -- 300Ω
LOS2: R39 -- 0Ω, R97 -- 300Ω
LOL1: R8 -- 0Ω, R98 -- 300Ω
LOL2: R38 -- 0Ω, R99 -- 300Ω
INTTX1B: R92 – 10KΩ, R42 -- 300Ω
INTTX2B: R94 – 10KΩ, R46 -- 300Ω
INTRX1B: R93 – 10KΩ, R43 -- 300Ω
INTRX2B: R95 – 10KΩ, R47 -- 300Ω
CMOS:
LOS1: R7 -- 300Ω, R96 – DNP
LOS2: R39 -- 300Ω, R97 – DNP
LOL1: R8 -- 300Ω, R98 – DNP
LOL2: R38 -- 300Ω, R99 – DNP
INTTX1B: R92 – DNP, R42 -- 300Ω
INTTX2B: R94 – DNP, R46 -- 300Ω
INTRX1B: R93 – DNP, R43 -- 300Ω
INTRX2B: R95 – DNP, R47 -- 300Ω
Signal
PWR
SI2CKP/N
SI2DP/N
SO2CKP/N
SO2DP/N
SI1CKP/N
SI1DP/N
SO1CKP/N
SO1DP/N
RXxP/N
CMIxP/N
ECLxP/N
Description
Power plane test points
Channel 2 transmit serial
clock / data input
Channel 2 receive serial
clock / data output
Channel 1 transmit serial
clock / data input
Channel 1 receive serial
clock / data output
Receive serial CMI or
LVPECL input
Transmit serial CMI data
output
Transmit
LVPECL data output
The demo boards are
serial
(NRZ)