M5373EVB Freescale Semiconductor, M5373EVB Datasheet - Page 23

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M5373EVB

Manufacturer Part Number
M5373EVB
Description
KIT EVAL FOR MCF537X
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
MPUr
Datasheet

Specifications of M5373EVB

Contents
Module and Misc Hardware
For Use With/related Products
MCF537x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
5.7.2
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Freescale Semiconductor
Num
DD1
DD2
DD3
DD4
DD5
DD6
DD7
SD_SDR_DQS
SD_DQS[3:2]
SD_BA[1:0]
SD_RAS,
SD_CAS,
SD_CSn,
Memories
Frequency of Operation
Clock Period
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS) Relative
to DQS (DDR Write Mode)
SD_CLK
SD_WE
SD_CLK
Delayed
A[23:0],
D[31:0]
SDDM
from
DDR SDRAM AC Timing Characteristics
(Measured at Output Pin)
(Measured at Input Pin)
NOTE: Data driven from memories relative
1
SD4
3
2
to delayed memory clock.
Characteristic
ROW
CMD
MCF537x ColdFire
3
4, 5
SD1
Table 11. DDR Timing Specifications
SD5
Figure 10. SDR Read Timing
®
COL
3/4 MCLK
Reference
Microprocessor Data Sheet, Rev. 4
Board Delay
Board Delay
tDQS
t
t
t
Symbol
SDCHACV
SDCHACI
CMDVDQ
t
t
t
DDCKH
DQDMV
t
t
DDCKL
SD10
DDCK
DDSK
WD1
SD2
SD6
SD9
12.5
0.45
0.45
Min
2.0
1.5
60
WD2
SD7
0.5 × SD_CLK
Electrical Characteristics
SD8
WD3
16.67
+ 1.0
Max
0.55
0.55
1.25
80
SD3
WD4
SD_CLK
SD_CLK
SD_CLK
Unit
Mhz
ns
ns
ns
ns
23

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