AD9861-50EB Analog Devices Inc, AD9861-50EB Datasheet - Page 31

• Manufacturer Part Number: AD9861-50EB
• Description: BOARD EVAL FOR AD9861-50
• Manufacturer: Analog Devices Inc

Specifications of AD9861-50EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9861-50

Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether
transmitting or receiving.
Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases)
Mode Name
FD
HD10
(Tx/ Rx = High)
HD10
(Tx/ Rx = Low)
HD20
(Tx/ Rx = High)
HD20
(Tx/ Rx = Low)
Clone Mode
(Tx/ Rx = High)
Clone Mode
(Tx/ Rx = Low)
Table 13 describes AD9861 pin function (when SPI programming is used) relative to flexible I/O mode, and for half-duplex modes
whether transmitting or receiving.
Table 13. AD9861 Pin Function vs. Interface Mode (Configured through the SPI Registers)
Mode Name
FD
HD10, Tx Mode
(Tx/ Rx = High)
HD10, Rx Mode
(Tx/ Rx = Low)
HD20, Tx Mode
(Tx/ Rx = High)
HD20, Rx Mode
(Tx/ Rx = Low)
Clone Mode ,
Tx Mode
(Tx/ Rx = High)
Clone Mode ,
Rx Mode
(Tx/ Rx = Low)
Summary of Flexible I/O Modes
FD Mode
The full-duplex (FD) mode can be configured by using mode
pins or with SPI programming. Using the SPI allows additional
configuration flexibility of the device.
FD mode is the only mode that supports full-duplex, receive,
and transmit concurrent operation. The upper 10-bit bus (U10)
is used to accept interleaved Tx data, and the lower 10-bit bus
(L10) is used to output interleaved Rx data. Either the Rx path
or the Tx path (or both) can be independently powered down
using either (or both) the RxPwrDwn and TxPwrDwn pins. FD
mode requires interpolation of 2× or 4×.
U10
Interleaved Tx Data
Interleaved Tx Data
MSB = RxSYNC
Others = Three-state
Tx_A Data
Rx_B Data
Clone mode not available without SPI.
Clone mode not available without SPI.
U10
Interleaved Tx Data
Interleaved Tx Data
MSB = RxSYNC
Other = Three-state
Tx_A Data
Rx_B Data
Interleaved Tx Data
Rx_B Data
MSB = TxSYNC
Others = Three-state
Interleaved Rx Data
Tx_B Data
Rx_A Data
L10
Interleaved Rx Data
L10
Interleaved Rx Data
MSB = TxSYNC
Others = Three-state
Interleaved Tx Data
Tx_B Data
Rx_A Data
MSB = TxSYNC
Others = Three-state
Rx_A Data
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IFACE1
Tx/ Rx = Tied High
Tx/ Rx = Tied Low
Tx/ Rx = Tied High
Tx/ Rx = Tied Low
TxSYNC
IFACE1
TxSYNC
Tx/ Rx = Tied High
Tx/ Rx = Tied Low
Tx/ Rx = Tied High
Tx/ Rx = Tied Low
Tx/ Rx = Tied High
Tx/ Rx = Tied Low
The following notes provide a general description of the FD
mode configuration. For more information, refer to Table 16.
Note the following about the Tx path in FD mode:
•
•
•
Interpolation rate of 2× or 4× can be programmed with
mode pins or SPI.
Max DAC update rate = 200 MSPS.
Max Tx input data rate = 80 MSPS/channel (160 MSPS
interleaved).
TxSYNC is used to direct Tx input data.
TxSYNC = high indicates channel Tx_A data.
TxSYNC = low indicates channel Tx_B data.
IFACE2
Buffered Rx Clock
10/ 20 Pin Control Tied High
10/ 20 Pin Control Tied High
10/ 20 Pin Control Tied Low
10/ 20 Pin Control Tied Low
IFACE2
Buffered System
Clock
Optional Buffered
System Clock
Optional Buffered
System Clock
Optional Buffered
System Clock
Optional Buffered
System Clock
Optional Buffered
System Clock
Optional Buffered
System Clock
IFACE3
Buffered Tx Clock
Buffered Tx Clock
Buffered Rx Clock
Buffered Tx Clock
Buffered Rx Clock
Buffered Tx Clock
Buffered Rx Clock
IFACE3
Buffered Tx Clock
Buffered Tx Clock
Buffered Rx Clock
Buffered Tx Clock
Buffered Rx Clock
AD9861