AD9861-50EB Analog Devices Inc, AD9861-50EB Datasheet - Page 36

• Manufacturer Part Number: AD9861-50EB
• Description: BOARD EVAL FOR AD9861-50
• Manufacturer: Analog Devices Inc

Specifications of AD9861-50EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9861-50

AD9861
SPI Register Map
Registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. The SPI allows access to many configurable options.
Detailed descriptions of the bit functions are found in Table 18.
Table 17. Register Map
Reg. Name
General
Clock Mode
Power-Down
RxA Power-Down 0x03
RxB Power-Down 0x04
Rx Power-Down
Rx Path
Rx Path
Rx Path
Rx path
Rx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
I/O Configuration 13
I/O Configuration 14
Clock
Clock
Auxiliary
Converters
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxADC
AuxDAC
Addr
0x00
0x01
0x02
0x05
0x06
0x07
0x08
0x09
0x0A
0B
0C
0D
0E
0F
10
11
12
15
16
17
18
19
1A
1B
1C
1D
1E
1F
22
23
24
25
26
28
29
Rx_A Analog
Rx_B Analog
Rx Analog Bias
DAC A Offset [9:2]
DAC A Offset [1:0]
DAC A Coarse Gain Control
DAC B Offset [1:0]
DAC B Coarse Gain Control
TxPGA Gain [7:0]
Complement
AuxADC A
AuxADC B
AuxADC B [9:2]
TxPwrDwn
7
SDIO BiDir
clk_mode[2:0]
Tx Analog
DAC B Offset [9:2]
Tx Twos
PLL Bypass
AuxDAC A FS [1:0]
Start Average
Start Average
AuxADC A2 [1:0]
AuxADC A2 [9:2]
AuxADC A1 [1:0]
AuxADC A1 [9:2]
AuxADC B [1:0]
AuxSPI Enable
AuxDAC A [7:0]
AuxDAC B [7:0]
AuxDAC C [7:0]
Slave Enable
AuxDAC C Sync
6
LSB First
Rx_A DC Bias
Rx_B DC Bias
RxRef
Rx Ultralow
Power Control
Rx Ultralow
Power Control
TxPGA Slave
Enable
Rx Twos
Complement
Sel 2not1
AuxDAC B Sync
TxPwrDwn
5
Soft Reset
DiffRef
Rx_A Twos
Complement
Rx_B Twos
Complement
Rx Ultralow
Power Control
Rx Ultralow
Power Control
DAC A Fine Gain [5:0]
DAC B Fine Gain [5:0]
Tx Inverse
Sample
Dig Loop On
ADC Clock Div
PLL to IFACE2
AuxDAC B FS [1:0]
Refsel B
AuxDAC A Sync
TxPwrDwn
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4
TxDigital
VREF
Rx_A Clk
Duty
Rx_B Clk
Duty
Rx Ultralow
Power Control
Rx Ultralow
Power Control
TxPGA Fast
Update
SpiFDnHD
Alt Timing Mode
3
RxDigital
Rx Ultralow
Power Control
SpiTxnRx
PLL Div5
AuxDAC C FS [1:0]
Start B
2
Enable IFACE2
clkout
PLL Power-
Down
Rx Ultralow
Power Control
SpiB10n20
PLL Multiplier [2:0]
PLL Slow
Number of AuxADC A Samples [2:0]
Number of AuxADC B Samples [2:0]
Refsel A
Update C
Power-Up C
1
Inv clkout
(IFACE3)
PLL Output
Disconnect
Interpolation Control [1:0]
SPI IO Control
AuxADC Ref
Enable
Select A
AuxADC Clock Div[1:0]
Update B
Power-Up B
DAC A Offset
Direction
DAC B Offset
Direction
SpiClone
AuxADC Ref
FS
Start A
Update A
Power-Up A
0