SI4112-EVB Silicon Laboratories Inc, SI4112-EVB Datasheet - Page 12
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SI4112-EVB
Manufacturer Part Number
SI4112-EVB
Description
BOARD EVALUATION FOR SI4112
Manufacturer
Silicon Laboratories Inc
Type
Synthesizerr
Datasheet
1.SI4112-EVB.pdf
(40 pages)
Specifications of SI4112-EVB
Contents
Board and CD-ROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SI4112
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
4 Layer FR4
GND
+5VCC
+3VDD
GND
Si41aj-PCB
Euro_term
JP1
HEADER 13X2
2
4
6
8
10
12
14
16
18
20
22
24
26
JP11
1
2
3
11
13
15
17
19
21
23
25
1
3
5
7
9
PCB1
+5VCC
top copper: 35 microns (1 oz final copper + plating thickness)
first dielectric: FR4, 210 microns, tolerance +/- 10%
ground: 35 microns
second dielectric: FR4, 1025 microns, tolerance +/- 20%
Vdd: 35 microns
third dielectric: FR4, 210 microns, tolerance +/- 10%
bottom copper: 35 microns
-----------------------------------------------------------------------
Total thickness: 1585 microns
+5VCC
+
C16
10uF
1
3
2
U11
LP2980AIM-3.0
Vin
ON/OFF
GND
R14 1k
Vout
N/C
5
4
C10
100pF
GND
PC_AUXOUT
PC_PWDNB
PC_SEND
PC_SDATA
PC_SCLK
+
C17
10uF
GND
GND
Reg
3V
Unreg
18
16
14
12
11
13
15
17
10
U10
74LVTH241
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
GND Vcc
Figure 12. Si4133 TSSOP (2 of 2)
JP4
1
2
3
1OE
2OE
1A1
1A2
1A3
1A4
2Y1
2Y2
2Y3
2Y4
2
4
6
8
9
7
5
3
1
19
20
C12
22nF
GND
10uF
C19
10uF
C15
+3VDD
+3VDDRF
+
+
GND
Note 1:
GND
+3VDD
+3VDD
Header test point spacing : 200 mil
R23
0R
R24 0R
C18
10uF
J2
+3VDD
+
ON
TCXO
J1
GPO
J3
GND
C13
22nF
OFF
GND
GND
GND
JP5
J4
SENB
C14
10uF
GPO
Enable
R19
47k
+
3
4
J5
SDATA
JP2
U12
13.0MHz TCXO
OUT
VDD
GND
AFC
PWDNB
GND
TCXO Footprint
J6
SCLK
R20
47k
2
1
GPO / External
PWDNB
JP7
R25 0R
6.5
2.6
JP8
GND
J7
AUXOUT
GND
GND
See
Note 1
VC
GND
1
1
See
Note 1
1.1
R22 0R
JP9
JP10
Units : mm
+3VDDRF
8.0
PWDNB
Enable
R26
n/f
GND
JP3
TCXO
XIN
+3VDDRF
EXT
GND
J8
JP6
External Reference
Input
R21
47k
C11 100pF
PWDNB
SENB
SDATA
SCLK
AUXOUT
XIN