4421-DKDB2 Silicon Laboratories Inc, 4421-DKDB2 Datasheet - Page 24

• Manufacturer Part Number: 4421-DKDB2
• Description: KIT DEV TEST EZRADIO SI4421 TRX
• Manufacturer: Silicon Laboratories Inc

Specifications of 4421-DKDB2

• Accessory Type: Test Card, Transceiver, 434MHz
• Wireless Frequency: 434 MHz
• Interface Type: SPI
• Modulation: FSK
• For Use With/related Products: EZRadio®
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12. PLL Setting Command
Bits 6-5 (ob1-ob0):
current of the CLK pin. Higher current provides faster rise and fall times but can cause interference.
Note: Needed for optimization of the RF performance. Optimal settings can vary according to the external load capacitance.
Bit 3 (dly): Switches on the delay in the phase detector when this bit is set.
Bit 2 (ddit): When set, disables the dithering in the PLL loop.
Bit 0 (bw0):
Note: POR default settings of the register were carefully selected to cover almost all typical applications. When changing these
13. Transmitter Register Write Command
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration
Setting Command (page 15).
Multiple Byte Write with Transmit Register Write Command:
Note: Alternately the transmit register can be directly accessed by nFFS (pin6).
Bit
Bit
(REGISTER IT
in TX mode*)
nSEL
SCK
SDI
SDO
values, examine thoroughly the output RF spectrum. For more information, contact Silicon Labs Support.
Note: *The transceiver is in transmit (TX) mode when bit er is cleared using the Power Management Command
15
15
1
1
14
14
T r a n s m i t R e g i s t e r W r i t e
1
0
PLL bandwidth can be set for optimal TX RF performance.
13
13
0
1
command
Microcontroller output clock buffer rise and fall time control. The ob1-ob0 bits are changing the output drive
12
12
0
1
bw0
11
11
1
1
0
1
10
10
Max bit rate [kbps]
1
0
ob1
9
0
9
0
1
1
0
TX BYTE1
86.2
256
ob0
8
0
8
0
X
1
0
Selected µC CLK frequency
t7
7
0
7
5 or 10 MHz (recommended)
Phase noise at 1MHz offset [dBc/Hz]
ob1
t6
6
2.5 MHz or less
6
3.3 MHz
ob0
t5
5
5
TX BYTE2
t4
4
1
4
-107
-102
dly
t3
3
3
ddit
t2
2
2
t1
1
1
1
bw0
TX BYTEn
t0
0
0
CC77h
B8AAh
POR
POR
Si4421
24