SI4703-B17-EVB Silicon Laboratories Inc, SI4703-B17-EVB Datasheet - Page 10

• Manufacturer Part Number: SI4703-B17-EVB
• Description: BOARD EVAL SI4703 VERSION B
• Manufacturer: Silicon Laboratories Inc
• Type: Tunerr

Specifications of SI4703-B17-EVB

• Frequency: 76MHz ~ 108MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Si4703
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si4702/03-C19
Table 7. 2-Wire Control Interface Characteristics
(V
10
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO
(START)
SCLK Input to SDIO
SDIO Input to SCLK
SDIO Input to SCLK
SCLK input to SDIO
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
D
= V
1. When V
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
3. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
4. As a 2-wire transmitter, the Si4702/03-C19 delays SDIO by a minimum of 300 ns from the V
5. The maximum t
A
until after the 1st start condition.
high) does not occur within 300 ns before the rising edge of RST.
comply with the 0 ns t
violated so long as all other timing parameters are met.
= 2.7 to 5.5 V, V
IO
= 0 V, SCLK and SDIO are low impedance.





HD:DAT
IO
Setup (STOP)
Setup
Hold (START)
Setup
Hold
= 1.5 to 3.6 V, T
HD:DAT
has only to be met when f
4,5
specification.
A
Symbol
t
t
t
t
t
= –20 to 85 °C)
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
t
f:OUT
HIGH
t
LOW
t
BUF
t
SCL
C
f:IN
r:IN
SP
b
SCL
Test Condition
Rev. 1.1
= 400 kHz. At frequencies below 400 KHz, t
1,2,3
20 + 0.1 C
20 + 0.1 C
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
—
—
0
0
b
b
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
IH
threshold of SCLK to
HD:DAT
Max
400
900
250
300
50
50
—
—
—
—
—
—
—
may be
Unit
kHz
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns