HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet - Page 2

• Manufacturer Part Number: HSP50415EVAL1
• Description: EVALUATION BOARD HSP50415VI
• Manufacturer: Intersil
• Type: Modulator, Demodulatorr

Specifications of HSP50415EVAL1

• For Use With/related Products: HSP50415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Getting Started
Installation Requirements
Software Installation
Obtain the latest version of the downloadable software from
‘www.intersil.com/commlink/download/hsp50415eval1’. The
software is packaged into an executable zip file format. Copy
the file onto the target computer from the website.
Windows 95
Windows 98
Windows NT
Hardware Description
Board Components
The evaluation board consists of three major components as
depicted in the block diagram:
1. A personal computer running Windows 95, Windows 98,
2. A 5V
1. Execute the ‘HSP50415.exe’ installation program. This
2. Select and execute ‘ste51en.exe.’ This program will install
1. Execute the ‘HSP50415.exe’ installation program. This
2. If the target computer’s operating system was loaded with
1. Execute the ‘HSP50415.exe’ installation program. This
2. Select and execute ‘ste51en.exe.’ This program will install
3. Execute ‘TDLPortIO.exe’ from the disk. ‘TDLPortIO.exe’
1. HSP50415 (U4): This is the wideband programmable
2. SRAM (U7). The board uses a 256K x 18 bits
or Windows NT with a bidirectional parallel port.
evaluation CCA by sourcing 1.0 amps.
program will create folder HSP50415 and install the
required files.
the required Windows scripting host.
program will create folder HSP50415 and install the
required files.
the default system configuration, it is not necessary to
select and execute “ste51en.exe.” This program would
have been part of the default. If scripting errors are
encountered, execute ‘ste51en.exe.’
program will create folder HSP50415 and install the
required files.
the required Windows scripting host.
installs the parallel port driver, a necessary component
for running the software under Windows NT. In order to
run ‘TDLPortIO.exe’ successfully you must have
administrator privileges on your NT machine, and have
the ‘DLLPortIO.dll’ and ‘DLLPortIO.sys’ files in the same
directory from which you are executing ‘TDLPortIO.exe’.
Upon completion, you must reboot in order for the driver
to take effect.
modulator device.
synchronous RAM to store digital data patterns for the In-
phase and Quadrature inputs to the HSP50415. The
SRAM is clocked with the same clock that strobes data
DC
power supply capable of supporting the
2
HSP50415EVAL1
Communication with the PC is achieved using the ‘EPP’
(Standard Parallel Port) handshake. Each of the evaluation
board’s two clocks can be either driven internally by U5 and
U6, or externally via SMA connectors J4 and J5. When
providing these clocks externally, 50 terminators for the
external clock sources must be enabled through jumpers
JP6 and JP7.
CPLD Registers
The CPLD contains three groups of registers, the first group
contains an Address register and a Data register for
implementing the EPP handshake. Note that the PC doesn’t
necessarily require an EPP, as the evaluation software will
emulate the EPP handshake. The second group of CPLD
registers is shown in Table 2. These registers can be
accessed from the evaluation software using the console
commands “pldread” and “pldwrite” or using scripts. The
third group of registers is shown in Table 3. These registers
can be accessed from the evaluation software using the
console commands “read” and “write” or using scripts. For
more details refer to the ‘Software Description’ section.
Hardware Configuration
Verify the following default jumper configurations per Table
1:
WARNING: Ensure care is utilized to prevent the application of
Software Description
The evaluation software provides a graphical user interface
that allows full control over the HSP50415 evaluation board.
Through the software, all operational modes of the
HSP50415 can be exerted, via the CPLD and SRAM. The
3. CPLD (U2): The CPLD’s main function is to interface
1. JP1 in position 1-2. (programming ‘norm’ mode).
2. JP-2 and JP-3 in position 1-2. (board address to 00).
3. JP4 has no jumper. (software controls the source of
4. JP5 in position 1-2. (HSP50415 REFLO enabled as the
5. JP6 has no jumper (for using the internal REFCLK).
6. JP7 has no jumper (for using the internal Clk).
7. Connect the 5V power supply to the evaluation board
8. Connect the supplied ribbon cable from the PC’s parallel
into the HSP50415 (DATACLK). The RAM can hold I/Q
stimulus patterns that are repeatable with no overhead.
between the HSP50415, the PC’s parallel port, and the
SRAM. The CPLD is in system re-programmable,
allowing for CCA configuration fielded upgrades.
DATACLK).
1.2V internal reference).
connector J1 using the supplied power cable. Ensure the
power supply can source 1.0 amps regulated at
5V
port to the evaluation board’s P1 connector ensuring the
arrow indicating pin one on the ribbon cable connector J1
and the CCA P1 are correctly mated.
DC
5%.
reverse polarity power to the CCA.