AD9869BCPZ Analog Devices Inc, AD9869BCPZ Datasheet
AD9869BCPZ
Specifications of AD9869BCPZ
Related parts for AD9869BCPZ
AD9869BCPZ Summary of contents
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FEATURES Low cost 3.3 V CMOS MxFE for broadband modems 12-bit DAC converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 17 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS, ADC converter − +48 ...
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AD9869 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications........................................................ 6 Digital Specifications ................................................................... 7 ...
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SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, f Table 1. Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full-Scale Output Current (IOUTP_FS) 2 Gain Error Offset Error Voltage ...
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AD9869 Parameter OSCIN Impedance 6 CLKOUT1 Jitter 7 CLKOUT2 Jitter 8 CLKOUT1 and CLKOUT2 Duty Cycle 1 See the Explanation of Test Levels section. 2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed ...
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Parameter RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Rx PATH COMPOSITE AC ...
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AD9869 POWER SUPPLY SPECIFICATIONS AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3 Table 3. Parameter SUPPLY VOLTAGES AVDD CLKVDD DVDD DRVDD IS_TOTAL (Total Supply Current) POWER CONSUMPTION (Analog Supply Current) AVDD CLKVDD ...
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DIGITAL SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, R Table 4. Parameter CMOS LOGIC INPUTS High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Capacitance CMOS LOGIC ...
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AD9869 HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 6. Parameter READ OPERATION 2 (See Figure 9) Output Data Rate Three-State ...
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ABSOLUTE MAXIMUM RATINGS Table 8. Parameter ELECTRICAL AVDD, CLKVDD Voltage DVDD, DRVDD Voltage RX+, RX−, REFT, REFB IOUTP+, IOUTP− IOUTN+, IOUTN− OSCIN, XTAL REFIO, REFADJ Digital Input and Output Voltage Digital Output Current ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction ...
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AD9869 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIO11/Tx[5] ADIO10/Tx[4] ADIO9/Tx[3] ADIO8/Tx[2] ADIO7/Tx[1] ADIO6/Tx[0] ADIO5/Tx[5] ADIO4/Tx[4] ADIO3/Rx[3] ADIO2/Rx[2] ADIO1/Rx[1] ADIO0/Rx[0] RXEN/RXSYNC TXEN/TXSYNC TXCLK/TXQUIET RXCLK Table 9. Pin Function Descriptions Pin No. Mnemonic 1 ADIO11 Tx[ ADIO10 to ADIO7 Tx[4:1] ...
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Pin No. Mnemonic 17, 64 DRVDD 18, 63 DRVSS 19 CLKOUT1 20 SDIO 21 SDO 22 SCLK 23 SEN 24 GAIN PGA[ PGA[4:0] 30 RESET 31, 34, 36, 39, 44, 47, 48 AVSS 32, 33 REFB, REFT ...
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AD9869 SERIAL PORT Table 10. SPI Register Mapping Address 1 (Hex) Bit Description SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 7 4-Wire SPI 6 SPI LSB First 5 Software Reset POWER CONTROL REGISTERS (Via PWRDWN Pin) 0x01 7 CLK Synthesizer ...
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Address 1 (Hex) Bit Description Tx/Rx PATH GAIN CONTROL 0x09 6 Enable SPI Rx Gain 5:0 Rx Gain Code 0x0A 6 Enable SPI Tx Gain 5:0 Tx Gain Code TxPGA AND RxPGA CONTROL 0x0B 6 PGA Code for Tx 5 ...
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AD9869 REGISTER MAP DESCRIPTION The AD9869 contains a set of programmable registers (see Table 10) that are used to optimize its numerous features, interface options, and performance parameters from its default register settings. Registers pertaining to similar functions have been ...
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Figure 5 illustrates the timing requirements for a write opera- tion to the SPI port. After the serial port enable ( SEN ) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of ...
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AD9869 DIGITAL INTERFACE The digital interface port is configurable for half-duplex or full- duplex operation by pin strapping the MODE pin low or high, respectively. In half-duplex mode, the digital interface port becomes a 12-bit bidirectional bus called the ADIO ...
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DIGITAL ASIC ADIO [11:0] Tx/Rx DATA[11:0] RXEN RXEN TXEN TXEN DACCLK TXCLK ADCCLK RXCLK CLKOUT OSCIN Figure 10. Example of a Half-Duplex Digital Interface with AD9869 Serving as the Slave Figure 11 shows a half-duplex interface with the AD9869 acting ...
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AD9869 The Rx[5:0] port operates in the following manner with the SPI register default settings: 1. Two consecutive nibbles of the Rx data are multiplexed together to form a 12-bit data-word in twos complement format. 2. The Rx data is ...
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RxPGA CONTROL The AD9869 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over − +48 dB with 1 dB resolution using a 6-bit word, and ...
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AD9869 TxPGA CONTROL The AD9869 also contains a digital PGA in the Tx path distri- buted between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and ...
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TRANSMIT PATH The transmit path of the AD9869 (or its related part, the AD9868) consists of a selectable digital 2×/4× interpolation filter, a 12-bit (or 10-bit) TxDAC, and a current-output amplifier, IAMP (see Figure 18). Note that the additional two ...
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AD9869 TxDAC AND IAMP ARCHITECTURE The Tx path contains a TxDAC with a current amplifier, IAMP. The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to an external load or ...
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Tx PROGRAMMABLE GAIN CONTROL TxPGA functionality is also available to set the peak output current from the TxDAC or IAMP. The TxDAC and IAMP are digitally programmable via the PGA[5:0] port or SPI over −7.5 dB ...
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AD9869 RECEIVE PATH The receive signal path for the AD9869 (or its related part, the AD9868) consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit) ADC (see Figure 24). Note that the additional two bits ...
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LOW-PASS FILTER The low-pass filter (LPF) provides a third-order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span. The first real pole is implemented within the first CPGA gain stage (see Figure ...
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AD9869 80MSPS MEASURED 25 80MSPS CALCULATED 50MSPS MEASURED 17 50MSPS CALCULATED 112 128 144 160 TARGET-DECIMAL EQUIVALENT Figure 29. Measured and Calculated f − ...
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Table 20 shows the SPI registers pertaining to the ADC. Table 20. SPI Registers for Rx ADC Address (Hex) Bit Description 0x04 4 ADC clock from PLL. 0x07 4 ADC low power mode. 0x13 2:0 ADC power bias adjust. AGC ...
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AD9869 CLOCK SYNTHESIZER The AD9869 generates all its internal sampling clocks, as well as two user-programmable clock outputs appearing at CLKOUT1 and CLKOUT2, from a single reference source (see Figure 32). The reference source can either be a fundamental frequency ...
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CLKOUT1 is a divided version of the VCO output and can be set submultiple integer DAC DAC or 3). Because this clock is derived from the same set of dividers used within the PLL ...
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AD9869 POWER CONTROL AND DISSIPATION POWER-DOWN The AD9869 provides the ability to control the power-on state of various functional blocks. The state of the PWRDWN pin, along with the contents of Register 0x01 and Register 0x02, allow two user-defined power ...
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For a Tx burst, the falling edge of TXEN is used to generate an internal delayed signal for powering down the Tx circuitry. Upon receipt of this signal, power-down of the Tx circuitry occurs within 100 ns. The user-programmable delay ...
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AD9869 Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD varies as a function of Register ...
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The ADC is based on a pipeline architecture with each stage consisting of a switched capacitor amplifier. Therefore, its performance vs. bias level is mostly dependent on the sample rate. Figure 38 shows how the typical current consumption seen at ...
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AD9869 A hardware reset ( RESET pin) or software reset (Bit 5 of Register 0x00) can be used to place the AD9869 into a known state of operation as determined by the state of the MODE and CONFIG pins. A ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9869BCPZ −40°C to +85°C 1 AD9869BCPZRL −40°C to +85° RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.50 0. 0.30 0.80 MAX ...
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AD9869 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06736-0-5/07(0) Rev Page ...