AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet
AD9869-EBZ
Specifications of AD9869-EBZ
Related parts for AD9869-EBZ
AD9869-EBZ Summary of contents
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... MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization. The AD9869 provides a highly integrated solution for many broadband modems available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (−40°C to +85°C). ...
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... AD9869 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications........................................................ 6 Digital Specifications ................................................................... 7 Serial Port Timing Specifications............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 8 Full-Duplex Data Interface (Tx and Rx Port) Timing Specifications ...
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... AD9869 Unit Bits MSPS μ dBm dBc dBc dBc dBc mA V dBm dBc ppm/ C Cycles f /f OUT DAC f /f OUT DAC dB Cycles ...
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... AD9869 Parameter OSCIN Impedance 6 CLKOUT1 Jitter 7 CLKOUT2 Jitter 8 CLKOUT1 and CLKOUT2 Duty Cycle 1 See the Explanation of Test Levels section. 2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and p-p differential analog input). 3 TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, f ...
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... MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80. IN Temp 25°C 25°C Full Full MSPS ADC 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C . ADC Rev Page AD9869 1 Test Level Min Typ Max III 63.1 III −67.2 IV 64.3 IV −67.3 III 41.8 III −67 III 58.6 III − ...
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... AD9869 POWER SUPPLY SPECIFICATIONS AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3 Table 3. Parameter SUPPLY VOLTAGES AVDD CLKVDD DVDD DRVDD IS_TOTAL (Total Supply Current) POWER CONSUMPTION (Analog Supply Current) AVDD CLKVDD (Digital Supply Current) DVDD DRVDD POWER CONSUMPTION (Half-Duplex Operation with f Tx Mode AVDD ...
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... Full Full Full Full Full Full Full Full Full ) Full DV ) Full EZ Rev Page Min Typ Max DRVDD − 0.7 0 DRVDD − 0.7 0.4 1.5/2.3 1.9/2.7 0.7/0.7 1.0/1 Test Level Min Typ AD9869 Unit V V μ Clock cycles Max Unit 32 MHz MHz ...
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... AD9869 HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 6. Parameter READ OPERATION 2 (See Figure 9) Output Data Rate Three-State Output Enable Time (t ) PZL Three-State Output Disable Time (t ) PLZ Rx Data Valid Time (t ...
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... Sample tested only. 125°C IV. Parameter is guaranteed by design and characterization 150°C testing. −65°C to +150°C V. Parameter is a typical value only. VI. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. ESD CAUTION Rev Page AD9869 ...
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... ADIO1 Rx[1] 12 ADIO0 Rx[0] 13 RXEN RXSYNC 14 TXEN TXSYNC 15 TXCLK TXQUIET 16 RXCLK PIN 1 3 IDENTIFIER AD9869 7 TOP VIEW 8 (Not to Scale Figure 2. Pin Configuration 1 Mode Description HD MSB of ADIO Buffer. FD MSB of Tx Nibble Input. HD Bit 10 to Bit 7 of ADIO Buffer. FD Bit 4 to Bit Nibble Input. ...
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... Digital Interface Mode Select Input, Low = HD, High = FD. Power-Up SPI Register Default Setting Input. Clock Oscillator/Synthesizer Supply Return. Crystal Oscillator Inverter Output. Crystal Oscillator Inverter Input. Clock Oscillator/Synthesizer Supply. Digital Supply Return. Digital Supply Input Clock Output ( 4). OSCIN Power-Down Input. Rev Page AD9869 ...
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... AD9869 SERIAL PORT Table 10. SPI Register Mapping Address 1 (Hex) Bit Description SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 7 4-Wire SPI 6 SPI LSB First 5 Software Reset POWER CONTROL REGISTERS (Via PWRDWN Pin) 0x01 7 CLK Synthesizer 6 TxDAC/IAMP 5 Tx Digital 4 REF 3 ADC CML 2 ADC ...
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... Analog loopback: ADC Rx data fed back to TxDAC. Digital loopback: Tx input data to Rx output port. Default setting is for high drive strength and IAMP enabled Standing current. Current bias setting for Rx path’s functional blocks. Refer to the Power Reduction Options section. AD9869 ...
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... The CONFIG pin can be used to select the default interpolation ratio of the Tx path and RxPGA gain mapping. SERIAL PORT INTERFACE (SPI) The serial port of the AD9869 has 3-wire or 4-wire SPI capability allowing read/write access to all registers that configure the device’s internal parameters. Registers pertaining to the SPI are listed in Table 11 ...
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... The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times SCLK t t LOW R/W Figure 5. SPI Write Operation Timing SCLK LOW R/W Figure 6. SPI 3-Wire Read Operation Timing SCLK t t LOW R Figure 7. SPI 4-Wire Read Operation Timing Rev Page AD9869 ...
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... TX3 TX4 master to the digital ASIC. An example of a slave configuration is shown in Figure 10. In this example, the AD9869 accepts all the clock and control signals from the digital ASIC. Because the sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must be at exactly the same frequency as the OSCIN signal ...
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... A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9869 to be completely powered down (including the clock synthesizer) while serving as the master. ...
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... The output driver strength can also be reduced for lower data rate applications. For the AD9869, the most significant nibble defaults to 6 bits, and the least significant nibble defaults to 4 bits. This can be changed so that the least significant nibble and most significant nibble have 5 bits each ...
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... RxPGA CONTROL The AD9869 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over − +48 dB with 1 dB resolution using a 6-bit word, and with setting corresponding p-p input signal. The 6-bit word is fed into a look-up table (LUT) that is used to distribute the desired gain over three amplification stages within the Rx path ...
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... AD9869 TxPGA CONTROL The AD9869 also contains a digital PGA in the Tx path distri- buted between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A 6-bit word is used to set the TxPGA attenuation according to the mapping shown in Figure 17 ...
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... TxDAC, and a current-output amplifier, IAMP (see Figure 18). Note that the additional two bits of resolution offered by the AD9869 result reduction in the pass- band noise floor. The digital interpolation filter relaxes the Tx analog filtering requirements by simultaneously reducing the images from the DAC reconstruction process while increasing the analog filter’ ...
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... AD9869 TxDAC AND IAMP ARCHITECTURE The Tx path contains a TxDAC with a current amplifier, IAMP. The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to an external load or fed into the IAMP for further amplification. The TxDAC and IAMP peak current outputs are digitally programmable over − ...
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... IOUTN+ IOUT PK IAMP TxDAC IOUTN– –7.5dB 0 TO –12dB IOUT = N × POUT PK Figure 23. Current-Mode Operation BIAS . Note that the V bias should not exceed 3.3 V. The × N × I × V IAMP CM AD9869 to 0 − AVDD × N × I BIAS T (IOUT ) × T × that is BIAS ...
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... AD9869 RECEIVE PATH The receive signal path for the AD9869 (or its related part, the AD9868) consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit) ADC (see Figure 24). Note that the additional two bits of resolution offered by the AD9869 result lower noise floor, depending on the RxPGA gain setting and LPF cutoff frequency ...
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... MHz @ 0 dB and MSPS) −3 dB ADC 1 can be used to estimate (128/target) × (f /80) ×(f /30 + 23.83) f −3dB_0dB ADC ADC range of 15 MHz to 35 MHz and an f −3 dB AD9869 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 ...
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... MSPS and RxPGA = 0 dB −3 dB ADC ANALOG-TO-DIGITAL CONVERTER (ADC) The AD9869 features a 12-bit analog-to-digital converter (ADC) capable MSPS. As shown in Figure 24, the ADC is driven by the SPGA stage, which performs both the sample-and-hold and the fine gain adjust functions. A buffer amplifier (not shown) isolates the last CPGA gain stage from the dynamic load presented by the SPGA stage ...
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... ADC clock cycles (1/f half-duplex interface, and 10.5 ADC clock cycles in the case of a full-duplex interface. This latency, along with the RxPGA settling time, should be considered to ensure stability of the AGC loop. Rev Page AD9869 ) in the case of a ADC ...
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... AD9869 CLOCK SYNTHESIZER The AD9869 generates all its internal sampling clocks, as well as two user-programmable clock outputs appearing at CLKOUT1 and CLKOUT2, from a single reference source (see Figure 32). The reference source can either be a fundamental frequency or an overtone quartz crystal connected between OSCIN and XTAL, with the parallel resonant load components specified by the crystal manufacturer ...
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... 2). With L set to 0, the output of CLKOUT2 is a delayed version of the signal appearing at OSCIN, exhibiting the same duty cycle characteristics. With L set the output of CLKOUT2 is a divided version of the OSCIN signal, exhibiting a near 50% duty cycle, but without having a deterministic phase relationship relative to CLKOUT1 (or RXCLK). Rev Page AD9869 , OSCIN ...
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... With MODE = 1 and CONFIG =1, Register 0x02 default settings are with all blocks powered off, with RXCLK providing a buffered version of the signal appearing at OSCIN. This setting results in the lowest power consumption upon power- up, while still allowing AD9869 to generate the system clock via a crystal. HALF-DUPLEX POWER SAVINGS Significant power savings can be realized in applications having a half-duplex protocol, allowing only the Rx path or Tx path to be operational at one time ...
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... To disable the fast power-down of the Tx circuitry and/or Rx circuitry, set Bit 1 and/or Bit POWER REDUCTION OPTIONS The power consumption of the AD9869 can be significantly reduced from its default setting by optimizing the power consumption vs. performance of the various functional blocks in the Tx signal path and Rx signal path. On the Tx path, ...
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... AD9869 Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits[7:5], while the remaining bits are maintained at their default settings of 0 ...
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... T 85°C, the maximum allowable power dissipation can be determined by the following equation: Assuming the IAMP common-mode bias voltage is operating off the same analog supply as the AD9869, the following equa- 101 tion can be used to calculate the maximum total current consumption, I ...
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... AD9869 A hardware reset ( RESET pin) or software reset (Bit 5 of Register 0x00) can be used to place the AD9869 into a known state of operation as determined by the state of the MODE and CONFIG pins offset calibration and filter tuning routine is also initiated upon a hardware reset, but not with a software reset ...
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... Figure 40. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ Rev Page 0.30 0.25 0.60 MAX 0.18 PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF Package Option CP-64-3 CP-64-3 AD9869 ...
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... AD9869 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06736-0-5/07(0) Rev Page ...