AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 31

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For a Tx burst, the falling edge of TXEN is used to generate an
internal delayed signal for powering down the Tx circuitry. Upon
receipt of this signal, power-down of the Tx circuitry occurs
within 100 ns. The user-programmable delay for the Tx path
power-down is meant to match the pipeline delay of the last Tx
burst sample such that power-down of the TxDAC and IAMP
does not impact its transmission. A 5-bit field in Register 0x03 sets
the delay from 0 to 31 TXCLK clock cycles, with the default
being 31 (0.62 μs with f
filter is automatically flushed with midscale samples prior to
power-down if the clock signal into the TXCLK pin is present
for 33 additional clock cycles after TXEN returns low. For an Rx
burst, the rising edge of TXEN is used to generate an internal
signal (with no delay) that powers up the Tx circuitry within 0.5 μs.
The Rx path power-on/power-off can be controlled by either
TXEN or RXEN by setting Bit 2 of Register 0x03. In the default
setting, the falling edge of TXEN powers up the Rx circuitry
within 2 μs, while the rising edge of TXEN powers down the Rx
circuitry within 0.5 μs. If RXEN is selected as the control signal,
its rising edge powers up the Rx circuitry, and the falling edge
powers it down. To disable the fast power-down of the Tx
circuitry and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0.
POWER REDUCTION OPTIONS
The power consumption of the AD9869 can be significantly
reduced from its default setting by optimizing the power
consumption vs. performance of the various functional blocks
in the Tx signal path and Rx signal path. On the Tx path,
minimum power consumption is realized when the TxDAC
output is used directly and its standing current is reduced to as
low as 1 mA. Although a slight degradation in THD performance
results at reduced standing currents, it often remains adequate
for most applications because the op amp driver typically limits
the overall linearity performance of the Tx path. The load
resistors used at the TxDAC outputs (IOUTP+ and IOUTP−)
can be increased to generate an adequate differential voltage
that can be further amplified via a power efficient op amp-
based driver solution. Figure 33 shows how the supply current
for the TxDAC is reduced from 55 mA to 14 mA as the standing
current is reduced from 12.5 mA to 1.25 mA. Further Tx power
savings can be achieved by bypassing or reducing the interpola-
tion factor of the digital filter as shown in Figure 34.
TXCLK
= 50 MSPS). The digital interpolation
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Power consumption on the Rx path can be achieved by reducing
the bias levels of the various amplifiers contained within the
RxPGA and ADC. As previously noted, the RxPGA consists of
two CPGA amplifiers and one SPGA amplifier. The bias levels
of each of these amplifiers, along with the ADC, can be controlled
via Register 0x13 as shown in Table 24. The default setting for
Register 0x13 is 0x00.
Table 24. SPI Register for RxPGA and ADC Biasing
Address (Hex)
0x07
0x13
Figure 33. Reduction in TxDAC Supply Current vs. Standing Current
Figure 34. Digital Supply Current Consumption vs. Input Data Rate
55
50
45
40
35
30
25
20
15
10
65
60
55
50
45
40
35
30
25
20
15
20
0
1
(DVDD = DRVDD = 3.3 V and f
4× INTERPOLATION
2
30
3
Bit
4
7:5
4:3
2:0
INPUT DATA RATE (MSPS)
4
1× (HALF-DUPLEX ONLY)
40
5
I
STANDING
6
Description
ADC low power.
CPGA bias adjust.
SPGA bias adjust.
ADC power bias adjust.
50
7
(mA)
OUT
8
2× INTERPOLATION
60
= f
9
DATA
10
/10)
70
11
AD9869
12
13
80