AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 29

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLKOUT1 is a divided version of the VCO output and can be
set to be a submultiple integer of f
or 3). Because this clock is derived from the same set of dividers
used within the PLL core, it is phase-locked to the dividers such
that its phase relationship relative to the signal appearing at
OSCIN (or RXCLK) can be determined upon power-up. In
addition, this clock has a near 50% duty cycle because it is
derived from the VCO. As a result, CLKOUT1 should be
selected before CLKOUT2 as the primary source for system
clock distribution.
DAC
(f
DAC
/2
R
, where R = 0, 1, 2,
Rev. 0 | Page 29 of 36
CLKOUT2 is a divided version of the reference frequency, f
and can be set to be a submultiple integer of f
where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is
a delayed version of the signal appearing at OSCIN, exhibiting
the same duty cycle characteristics. With L set to 1 or 2, the output
of CLKOUT2 is a divided version of the OSCIN signal, exhibiting
a near 50% duty cycle, but without having a deterministic phase
relationship relative to CLKOUT1 (or RXCLK).
OSCIN
(f
OSCIN
AD9869
/2
L
,
OSCIN
,