AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 33

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ADC is based on a pipeline architecture with each stage
consisting of a switched capacitor amplifier. Therefore, its
performance vs. bias level is mostly dependent on the sample
rate. Figure 38 shows how the typical current consumption seen
at AVDD varies as a function of Register 0x13, Bits[2:0] and
sample rate, while the remaining bits are maintained at the
default setting of 0. Setting Bit 4 or Register 0x07 corresponds
to the 011 setting, and the settings of 101 and 111 result in
higher current consumption. Figure 39 shows how the SNR and
THD performance are affected for a 10 MHz sine wave input
for the lower power settings as the ADC sample rate is swept
from 20 MHz to 80 MHz.
A sine wave input is a standard and convenient method of
analyzing the performance of a system. However, the amount of
power reduction that is possible is application dependent, based
on the nature of the input waveform (such as frequency content,
and peak-to-rms ratio), the minimum ADC sample, and the
minimum acceptable level of performance. Thus, it is advisable
that power-sensitive applications optimize the power bias setting
of the Rx path using an input waveform that is representative of
the application.
Figure 39. SNR and THD Performance vs. f
Figure 38. AVDD Current vs. ADC Bias Setting and Sample Rate
61
60
59
58
57
56
55
54
53
52
51
220
210
200
190
180
170
160
150
140
130
120
20
20
RxPGA = 0 dB, f
30
30
40
SAMPLE RATE (MSPS)
40
SAMPLE RATE (MSPS)
IN
= 10 MHz, AIN = −1 dBFS
101 OR 111
THD-00
THD-01
THD-10
THD-11
100
50
50
001
011
010
000
ADC
60
and ADC Bias Setting with
60
101
70
SNR-00
SNR-01
SNR-10
SNR-11
70
80
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
80
Rev. 0 | Page 33 of 36
POWER DISSIPATION
The power dissipation of the AD9869 can become quite high in
full-duplex applications in which the Tx path and Rx path are
simultaneously operating with nominal power bias settings. In
fact, some applications that use the IAMP may need to either
reduce its peak power capabilities or reduce the power
consumption of the Rx path so that the device’s maximum
allowable power consumption, P
P
does not exceed 125°C at an ambient temperature of 85°C. This
specification is based on the 64-lead LFSCP having a thermal
resistance, θ
30.8°C/W if the heat slug remains unsoldered.) If a particular
application’s maximum ambient temperature, T
85°C, the maximum allowable power dissipation can be
determined by the following equation:
Assuming the IAMP common-mode bias voltage is operating
off the same analog supply as the AD9869, the following equa-
tion can be used to calculate the maximum total current
consumption, I
With an ambient temperature of up to 85°C, I
If the IAMP is operating off a different supply or in the voltage
mode configuration, first calculate the power dissipated in the
IAMP, P
Equation 11.
Figure 33, Figure 34, Figure 36, and Figure 38 can be used to
calculate the current consumption of the Rx and Tx paths for a
given setting.
MODE SELECT UPON POWER-UP AND RESET
The AD9869 power-up state is determined by the logic levels
appearing at the MODE and CONFIG pins. The MODE pin is
used to select a half- or full-duplex interface by pin strapping it
low or high, respectively. The CONFIG pin is used in conjunc-
tion with the MODE pin to determine the default settings for
the SPI registers as outlined in Table 10.
The intent of these particular default settings is to allow some
applications to avoid using the SPI (disabled by pin strapping
SEN high), thereby reducing implementation costs. For
example, setting MODE low and CONFIG high configures the
AD9869 to be backward compatible with the AD9975, while
setting MODE high and CONFIG low makes it backward
compatible with the AD9875. Other applications must use the
SPI to configure the device.
MAX
P
I
is specified at 1.66 W to ensure that the die temperature
MAX
MAX
IAMP
= (P
= 1.66 + (85 − T
, using Equation 3, and then recalculate I
JA
, of 24°C/W with its heat slug soldered. (The θ
MAX
MAX
− P
, of the IC:
IAMP
)/3.47
A
)/24
MAX
, is not exceeded.
MAX
A
, falls below
is 478 mA.
AD9869
MAX
using
JA
(10)
(11)
is