HSP50214BVIZ Intersil, HSP50214BVIZ Datasheet - Page 30

• Manufacturer Part Number: HSP50214BVIZ
• Description: IC DOWNCONVERTER 14BIT 120-MQFP
• Manufacturer: Intersil

Specifications of HSP50214BVIZ

• Function: Downconverter
• Rf Type: AMPS, CDMA, GSM, TDMA
• Package / Case: 120-MQFP, 120-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cartesian to Polar Converter
The Cartesian to Polar converter computes the magnitude
and phase of the I/Q vector. The I and Q inputs are 18 bits.
The converter phase output is 18-bits (truncated) with the 16
MSB’s routed to the output formatter and all 18-bits routed to
the frequency discriminator. The 16-bit output phase can be
interpreted either as two’s complement (-0.5 to
approximately 0.5) or unsigned (0.0 to approximately 1.0),
as shown in Figure 28. The phase conversion gain is 1/2π.
The phase resolution is 16-bits. The 16-bit magnitude is
unsigned binary format with a range from 0 to 2.32. The
magnitude conversion gain is 1.64676. The magnitude
resolution is 16 bits. The MSB is always zero.
Table 11 details the phase and magnitude weighting for the
16-bits output from the PDC.
FIGURE 28. PHASE BIT MAPPING OF COORDINATE
8000
±
7fff
π
15 (MSB)
0 (LSB)
BIT
14
13
12
10
11
9
8
7
6
5
4
3
2
1
4000
TABLE 11. MAG/PHASE BIT WEIGHTING
bfff
CONVERTER OUTPUT
+
-
π/2
π/2
Q
c000
3ff f
I
0000
ffff
0
MAGNITUDE
2
2
(Always 0)
2
2
2
2
30
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
-1
-2
-3
-4
-5
-6
-7
-8
-9
1
0
8000
7fff
π
4000
180
90
45
22.5
11.25
5.625
2.8125
1.40625
0.703125
0.3515625
0.17578125
0.087890625
0.043945312
0.021972656
0.010986328
0.005483164
bfff
3π/2
π/2
PHASE (
Q
c000
3fff
I
0000
ffff
o
0
)
HSP50214B
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the output formatter or frequency discriminator.
If a new input sample arrives before the end of the 17 cycles,
the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in resolution. Table 12 details the
exact resolution that can be obtained with a fixed number of
clock cycles up to the required 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
In the HSP50214, the input to the coordinate converter I/Q to
|r|/θ) block is 18-bits. If the signal range is large and the AGC
is not used, the quantization noise can become a
contributing factor in the phase and frequency computations.
For example, if the signal range is 84dB and the maximum
signal is set at full scale, the minimum signal would have
only 4-bits each for I and Q.
In the HSP50214B, an additional data path option was
added that allows the output of the 255 tap programmable
FIR filter to be routed directly to the coordinate converter.
Rather than having to select only 18-bits out of the available
26 bit output, all 26-bits of the FIR output are routed to the
coordinate converter. This change eliminates quantization
effects to give more accuracy in the phase and frequency
discriminator outputs. The AGC settling time is not a factor
because the AGC is effectively bypassed for the magnitude,
phase, and frequency computations.
NOTE: The most significant 18-bits of the computed phase are
†
Assumes ±180
TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES
CLOCKS
10
12
13
14
15
16
17
11
6
7
8
9
still routed to the discriminator.
o
MAGNITUDE
= f
ERROR
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
(% f
S
0.065
0.016
0.004
.
S
)
ERROR
(DEG.)
0.00175
PHASE
0.0035
0.056
0.028
0.014
0.007
0.45
0.22
0.11
3.5
1.8
0.9
†
ERROR
PHASE
(% f
0.062
0.016
0.008
0.004
0.002
0.001
0.25
0.12
0.03
0.5
May 1, 2007
2
1
FN4450.4
S
)