SX1210I084T Semtech, SX1210I084T Datasheet - Page 51

• Manufacturer Part Number: SX1210I084T
• Description: IC SINGLE-CHIP RECEIVER 32-TQFN
• Manufacturer: Semtech

Specifications of SX1210I084T

• Frequency: 863MHz ~ 960MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: Alarm Systems, Communication Systems
• Current - Receiving: 3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

The detailed description of the IRQParam register is given in Table 23.
Table 23: IRQParam Register Description
Rev 2– Sept 8
ADVANCED COMMUNICATIONS & SENSING
Name
Rx_stby_irq_0
Rx_stby_irq_1
Fifofull
/Fifoempty
Fifo_overrun_clr
Fifo_fill_method
Fifo_fill
6.3. Interrupt Configuration Parameters - IRQParam
th
, 2008
Bits
7-6
5-4
2
1
0
7
6
Address
(d)
13
13
13
13
13
14
14
RW
r/w
r/w
r
r
r/w/
c
r/w
r/w/
c
Description
IRQ_0 source in Rx and Standby modes:
If Data_mode(1:0) = 00 (Continuous mode):
00
01
10
11
If Data_mode(1:0) = 01 (Buffered mode):
00
01
10
11
If Data_mode(1:0) = 1x (Packet mode):
00
01
10
11
*also available in Standby mode (Cf sections 5.4.3 and 5.5.6)
IRQ_1 source in Rx and Standby modes:
If Data_mode(1:0) = 00 (Continuous mode):
xx
If Data_mode(1:0) = 01 (Buffered mode):
00
01
10
11
If Data_mode(1:0) = 1x (Packet mode):
00
01
10
11
*also available in Standby mode (Cf sections 5.4.3 and 5.5.6)
Fifofull IRQ source
Goes high when FIFO is full.
/Fifoempty IRQ source
Goes low when FIFO is empty
Goes high when an overrun error occurred. Writing a 1 clears flag and FIFO
FIFO filling method (Buffered mode only):
0
1
FIFO filling status/control (Buffered mode only):
Goes high when FIFO is being filled (sync word has been detected)
Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
If Fifo_fill_method = ‘0’: (d)
Automatically starts when a sync word is detected (d)
Manually controlled by Fifo_fill
DCLK
Sync (d)
RSSI
Sync
Sync
- (d)
Write_byte
/Fifoempty*
Sync
Payload_ready (d)
Write_byte
/Fifoempty*
Sync or Adrs_match (the latter if address filtering is enabled)
- (d)
Fifofull*
RSSI
Fifo_threshold*
CRC_ok (d)
Fifofull*
RSSI
Fifo_threshold*
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