SX1210 SEMTECH [Semtech Corporation], SX1210 Datasheet
SX1210
Related parts for SX1210
SX1210 Summary of contents
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... General Description The SX1210 is a low cost single-chip receiver operating in the frequency ranges from 863-870, 902- 928 MHz and 950-960 MHz. The SX1210 is optimized for very low power consumption (3mA). It incorporates a baseband demodulator with data rates up to 200 kb/s. Data handling features include a sixty-four byte FIFO, packet handling, CRC and data whitening processing ...
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... Sensitivity vs. LO Drift.........................................................66 7.6.3. Sensitivity vs. Receiver BW ................................................67 7.6.4. Sensitivity Stability over Temperature and Voltage ............68 7.6.5. Sensitivity vs. Bit Rate ........................................................68 7.6.6. Adjacent Channel Rejection................................................69 8. Packaging Information ..............................................................71 8.1. Package Outline Drawing ......................................................71 8.2. PCB Land Pattern ..................................................................71 8.3. Tape & Reel Specification......................................................72 9. Revision History ........................................................................73 10. Contact Information.................................................................73 Page SX1210 www.semtech.com ...
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... Figure 15: RSSI IRQ Timings ...................................................... 22 Figure 16: OOK Demodulator Description ................................... 23 Figure 17: Floor Threshold Optimization...................................... 24 Figure 18: BitSync Description..................................................... 25 Figure 19: SX1210’s Data Processing Conceptual View ............. 28 Figure 20: SPI Interface Overview and uC Connections ............. 29 Figure 21: Write Register Sequence ............................................ 30 Figure 22: Read Register Sequence............................................ 31 Figure 23: Read Bytes Sequence (ex: 2 bytes) ........................... 31 Figure 24: FIFO and Shift Register (SR) ...
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... ADVANCED COMMUNICATIONS & SENSING Index of Tables Table 1: Ordering Information ........................................................ 1 Table 2: SX1210 Pinouts ............................................................... 7 Table 3: Absolute Maximum Ratings ............................................. 8 Table 4: Operating Range.............................................................. 8 Table 5: Power Consumption Specification ................................... 8 Table 6: Frequency Synthesizer Specification............................... 9 Table 7: Receiver Specification.................................................... 10 Table 8: Digital Specification........................................................ 11 Table 9: MCParam_Freq_band Setting ....................................... 15 Table 10: Operating Modes ......................................................... 27 Table 11: Pin Configuration vs. Chip Mode ................................. 27 Table 12: Data Operation Mode Selection ...
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... Semtech website for the latest updates or errata. 1. General Description The SX1210 is a single chip FSK and OOK receiver capable of operation in the 863-870 MHz and 902-928 MHz license free ISM frequency bands, as well as the 950 - 960 MHz frequency band. It complies with both the relevant European and North American standards, EN 300-220 V2 ...
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... ADVANCED COMMUNICATIONS & SENSING 1.2. Pin Diagram The following diagram shows the pins arrangement of the QFN package, top view. Notes: yyww refers to the date code ------ refers to the lot number th Rev 2– Sept 8 , 2008 Figure 2: SX1210 Pin Diagram Page SX1210 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 1.3. Pin Description Table 2: SX1210 Pinouts Number 0 1 TEST5 2 TEST1 3 VR_VCO 4 VCO_M 5 VCO_P TEST6 9 TEST7 10 XTAL_P 11 XTAL_M 12 TEST0 13 TEST8 14 NSS_CONFIG 15 NSS_DATA CLKOUT 20 21 IRQ_0 22 IRQ_1 23 PLL_LOCK 24 TEST2 25 TEST3 26 27 VR_1V 28 VR_DIG 29 30 TEST4 31 32 Note: pin 13 (Test 8) can be used as a manual reset trigger. See section 7.4.2 for details on its use. ...
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... ADVANCED COMMUNICATIONS & SENSING 2. Electrical Characteristics 2.1. ESD Notice The SX1210 is a high performance radio frequency device. It satisfies: Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model), except on pins 3-4-5-27-28-31-where it satisfies Class 1A. Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins. ...
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... Variable, depending on the - frequency. (1) From Sleep mode - From Stby mode - 200 kHz step - 1 MHz step - 5 MHz step - 7 MHz step - 12 MHz step - 20 MHz step - 27 MHz step - Page SX1210 Typ Max Unit - 870 MHz - 928 MHz - 960 MHz - 200 Kb Kb/s 50 200 kHz 12.8 ...
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... MHz offset From ready From Stby to Rx ready 200 kHz step 1MHz step 5MHz step 7MHz step 12MHz step 20MHz step 27MHz step From Rx ready Ranging from sensitivity Page SX1210 Typ Max Unit - -107 - dBm - -103 - dBm - -105 ...
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... NSS_DATA rising to falling edge. Note: on pin 10 (XTAL_P) and 11 (XTAL_N), maximum voltages of 1.8V can be applied. th Rev 2– Sept 8 , 2008 Conditions Min 0.8*VDD - Imax=1mA 0.9*VDD Imax=-1mA - - - 2 250 312 500 625 500 625 Page SX1210 Typ Max Unit - - V - 0.2*VDD 0.1*VDD MHz - 1 MHz - - µ ...
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... This section describes in depth the architecture of this ultra low-power receiver: LNA RFI LO1 Rx XTAL_P Frequency Synthesizer XO XTAL_M 3.1. Power Supply Strategy To provide stable sensitivity and linearity characteristics over a wide supply range, the SX1210 is internally regulated. This internal regulated power supply structure is described below: th Rev 2– Sept 8 , 2008 RSSI LO2 ...
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... These decoupling components are recommended for any design. 3.2. Frequency Synthesis Description The frequency synthesizer of the SX1210 is a fully integrated integer-N type PLL. The PLL circuit requires only five external components for the PLL loop filter and the VCO tank circuit. ...
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... The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose operation is discussed in the following section. Figure 5 shows a block schematic of the SX1210 PLL. Here the crystal reference frequency and the software controlled dividers R, P and S determine the output frequency of the PLL ...
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... LNA input and VCO. For best performance wound type inductors, with tight tolerance, should be used as described in section 7.5.3. 3.2.5.1. SW Settings of the VCO To guarantee the optimum operation of the VCO over the SX1210’s frequency and temperature ranges, the following settings should be programmed into the SX1210: Target channel ...
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... SX1210. 3.2.7. PLL Lock Detection Indicator The SX1210 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions. The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a “1” to this same register. ...
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... LO1 Rx RF IF1 3.3.1. Architecture The SX1210 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9 (approximately 100MHz). The second down-conversion down-converts the I and Q signals to base band in the case of the FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver. LO2 Second ...
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... Low-pass filter for FSK ( RXParam_PolyFilt_on=’’0’’ Polyphase filter for OOK ( RXParam_PolyFilt_on=’’1’’ ) the polyphase filter - Figure 11: Active Channel Filter Description Page ButterFilt f f requency C Canceled side of f requenc y www.semtech.com SX1210 ...
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... Rev 2– Sept 8 , 2008 ⎡ ⎤ Fdev ⎢ ⎥ FSK ⎣ ⎦ 2 > FSK drifts OOK Tbit = fo 100 kHz = RXParam _ PolypFilt " 0011 " − > OOK drifts Page SX1210 www.semtech.com ...
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... Val (RXParam_ButterFilt) [d] Figure 12: Butterworth Filter's Actual BW Polyphase Filter's BW, OOK 450 400 350 300 250 200 150 100 Val (RXParam_ButterFilt [d] RXParam_PolypFilt="0011" Figure 13: Polyphase Filter's Actual BW Page SX1210 Actual Theoretical Actual Theoretical www.semtech.com ...
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... RSSI IRQ Source The SX1210 can also be used to detect a RSSI level above a pre-configured threshold. The threshold is set in IRQParam_RSSI_irq_thresh and the IRQ status stored in IRQParam_RSSI_irq (cleared by writing a “1”). An ...
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... Its outputs can be fed to the Bit Synchronizer to recover the timing information. The user can also use the raw, unsynchronized, output of the FSK demodulator in Continuous mode. The FSK demodulator of the SX1210 operates most effectively for FSK signals with a modulation index greater than or equal to two: 3 ...
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... Rev 2– Sept 8 , 2008 Zoom Zoom Decay defined in RXPAram_OOK_thresh_step Period as defined in RXParam_OOK_thresh_dec_period Figure 16: OOK Demodulator Description Page SX1210 ‘’Peak -6dB’’ Threshold ‘’Floor’’ threshold defined by MCParam_OOK_floor_thresh Noise floor of receiver Time Fixed 6dB difference www.semtech.com ...
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... Rev 2– Sept 8 , 2008 NS & SENSING Set SX1210 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default RXParam_OOK_thresh setting No input signal Continuous Mode Monitor DATA pin (pin 20) Increment MCParam_OOK_floor_thres Glitch activity Optimization complete Figure 17: Floor Threshold Optimization Page ...
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... MCParam_BR. For a given bit rate, this parameter is determined by: th Rev 2– Sept 8 , 2008 = ⇒ _ OOK _ cutoff 00 = ⇒ _ OOK _ cutoff 11 output DATA mode DCLK IRQ_1 Figure 18: BitSync Description F = XTAL MCParam Page Fcutoff π Fcutoff π www.semtech.com SX1210 ...
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... Subsequent data transitions will preserve this centering. This has two implications: Firstly, if the Bit Rates of Transmitter and Receiver are known to be the same, the SX1210 will be able to receive an infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction. If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the ...
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... ADVANCED COMMUNICATIONS & SENSING 4. Operating Modes This section summarizes the settings for each operating mode of the SX1210, and explains the functionality available and the timing requirements for switching between modes. 4.1. Modes of Operation Table 10: Operating Modes Mode MCParam_Chip_mode Sleep 000 Standby 001 ...
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... Overview 5.1.1. Block Diagram Figure 19, illustrates the SX1210 data processing circuit. Its role is to interface the data from the demodulator and the uC access points (SPI, IRQ and DATA pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. ...
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... SPI Interface 5.2.1.1. Overview As illustrated in the Figure 20 below, the SX1210’s SPI interface consists of two sub blocks: SPI Config: used in all data operation modes to read and write the configuration registers which control all the parameters of the chip (operating mode, bit rate, etc...) SPI Data: used in Buffered and Packet mode to read data bytes from the FIFO ...
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... A1, the current content of A1 can be read by the uC. (In)/(Out) refers to SX1210 side Note that when writing more than one register successively not compulsory to toggle NSS_CONFIG back high between two write sequences. The bytes are alternatively considered as address and value. In this instance, all new values will become effective on rising edge of NSS_CONFIG ...
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... Figure 22: Read Register Sequence byte read D1(4) D1(3) D1(2) D1(1) D1(0) HZ Figure 23: Read Bytes Sequence (ex: 2 bytes) Page Current value at address byte read D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) SX1210 www.semtech.com ...
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... Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared. Fifo_threshold: Fifo_threshold interrupt source’s behavior can be programmed via MCParam_Fifo_thresh (B value). This behavior is illustrated in Figure 25. th Rev 2– Sept 8 , 2008 byte1 byte0 8 SR (8bits) 1 MSB Figure 24: FIFO and Shift Register (SR) Page SX1210 FIFO LSB www.semtech.com ...
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... Sync word. th Rev 2– Sept 8 , 2008 B+1 Rx & Stby Figure 25: FIFO Threshold IRQ Source Behavior Comments In Packet & Buffered modes FIFO can be read in Stby after Rx Bit N-1 = Bit N = Sync_value[1] Sync_value[0] Figure 26: Sync Word Recognition Page SX1210 # of bytes in FIFO www.semtech.com ...
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... Packet Handler The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 5.2.5. Control The control block configures and controls the full chip’s behavior according to the settings programmed in the configuration registers. th Rev 2– Sept 8 , 2008 Page SX1210 www.semtech.com ...
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... DATA pin (20). The SPI Data, FIFO and packet handler are thus inactive. Rx Data Rx SYNC RECOG. Datapath th Rev 2– Sept 8 , 2008 SX1210 CONTROL Figure 27: Continuous Mode Conceptual View Page SX1210 DATA IRQ_0 IRQ_1(DCLK) SPI NSS_CONFIG CONFIG SCK MOSI MISO www.semtech.com ...
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... The tables below give the description of the interrupts available in Continuous mode. Table 15: Interrupt Mapping in Continuous Rx Mode Note: In Continuous mode, no interrupt is available in Stby mode th Rev 2– Sept 8 , 2008 Figure 28: Rx Processing in Continuous Mode Rx_stby_irq_0 Rx 00 (d) Sync 01 RSSI IRQ_0 1x - DCLK IRQ_1 Page SX1210 www.semtech.com ...
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... MISO read register access is needed. In this case, pull-up to VDD through a 100 kΩ resistor. In addition, NSS_DATA pin (unused in continuous mode) should be pulled-up to VDD through a 100 kΩ resistor. Please refer to Table 11 for SX1210’s pins configuration 5.3.5. Continuous Mode Example Configure all data processing related registers listed below appropriately. In this example we assume that both Bit synchronizer and Sync word recognition are on ...
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... FIFO and accessed via the SPI Data interface. This frees the uC for other tasks between processing data from the SX1210, furthermore it simplifies software development and reduces uC performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive. ...
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... Sync ( Write_byte 10 /Fifoempty 11 Sync 00 ( Fifofull 10 RSSI 11 Fifo_threshold Page SX1210 b10 b11 b12 b13 b14 b15 b14 b13 b12 b11 b10 Stby - - /Fifoempty - - Fifofull - Fifo_threshold www.semtech.com b16 b15 ...
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... IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating. In addition, DATA pin (unused in buffered mode) should be pulled-up to VDD through a 100 kΩ resistor. Please refer to Table 11 for the SX1210’s pin configuration. 5.4.5. Buffered Mode Example Configure all data processing related registers listed below appropriately. In this example we assume Sync word recognition is on and Fifo_fill_method=0 ...
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... FIFO and accessed via the SPI Data interface. In addition, the SX1210’s packet handler performs several packet oriented tasks such as Preamble and Sync word extraction, CRC check, dewhitening of data, address filtering, etc. This simplifies still further software and reduces uC overhead by performing these repetitive tasks within the RF chip itself ...
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... Optional Address byte (Node ID). Message data. Optional 2-bytes CRC checksum. th Rev 2– Sept 8 , 2008 Optional DC free data decoding CRC checksum calculation Sync Word Address Message bytes byte 0 to (FIFO size) bytes Payload/FIFO Figure 34: Fixed Length Packet Format Page SX1210 CRC 2-bytes www.semtech.com ...
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... Rx mode if required. (e. Stby to get payload). FIFO must be empty for a new packet reception to start. 5.5.4. Packet Filtering SX1210’s packet handler offers several mechanisms for packet filtering ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.4.1. Sync Word Based Sync word filtering/recognition is automatically enabled in Packet mode ...
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... On your Tx side a two byte CRC checksum should be calculated on the payload part of the packet and appended to the end of the message. On SX1210 (Rx side) the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in the PKTParam_CRC_status bit and CRC_OK IRQ source ...
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... Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the SX1210 (Rx side) using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ datarate i ...
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... Payload_ready 01 Write_byte 10 /Fifoempty 11 Sync or Adrs_match* 00 (d) CRC_OK 01 Fifofull 10 RSSI 11 Fifo_threshold SX1210 IRQ_0 IRQ_1 NSS_CONFIG NSS_DATA SCK MOSI MISO Figure 39: uC Connections in Packet Mode Page ite Stby - - /Fifoempty - - Fifofull - Fifo_threshold uC www.semtech.com SX1210 0 X ...
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... ADVANCED COMMUNICATIONS & SENSING IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating. In addition, DATA pin (unused in packet mode) should be pulled-up to VDD through a 100 kΩ resistor. Please refer to Table 11 for the SX1210’s pin configuration. th Rev 2– Sept 8 ...
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... Enables Manchester decoding Length in fixed format, max length in variable format Defines node address for address filtering Defines packet format (fixed or variable length) Enables de-whitening process Enables CRC calculation/check Enables and defines address filtering Enables FIFO autoclear if CRC failed Page SX1210 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 6. Configuration and Status Registers 6.1. General Description Table 21 sums-up the control and status registers of the SX1210: Table 21: Registers List Name Size MCParam IRQParam RXParam SYNCParam Reserved OSCParam PKTParam 6.2. Main Configuration Register - MCParam The detailed description of the MCParam register is given in Table 22 ...
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... P counter, active when RPS_select=”1” r/w (d): 62h; default values of R2, P2, S2 generate 920.0 MHz in FSK mode S counter, active when RPS_select=”1” r/w (d): 32h; default values of R2, P2, S2 generate 920.0 MHz in FSK mode Reserved r/w (d): “00111000” Page SX1210 Data Operation Mode Continuous (d) Buffered Packet www.semtech.com ...
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... Manually controlled by Fifo_fill FIFO filling status/control (Buffered mode only): If Fifo_fill_method = ‘0’: (d) r/w/ c Goes high when FIFO is being filled (sync word has been detected) Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0) Page SX1210 www.semtech.com ...
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... Writing ‘1’ clears the bit PLL status: r/w/ 0 not locked c 1 locked Writing a ‘1’ clears the bit PLL_lock detect flag mapped to pin 23: r/w 0 Lock detect disabled, pin 23 is High-Z 1 Lock detect enabled(d) RSSI threshold for interrupt (coded as RSSI) (d): “00000000” Page SX1210 www.semtech.com ...
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... Sync word recognition: r/w 0 off ( Sync word size bits r bits 10 24 bits 11 32 bits (d) Number of errors tolerated in the Sync word recognition error (d) r error 10 2 errors 11 3 errors Reserved r/w (d):”0” Page SX1210 + 1 Val ( ButterFilt ) . 8 ( PolypFilt _ center ) 8 www.semtech.com ...
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... Byte of Sync word (d): “00000000” Byte of Sync word (only used if Sync_size ≠ 00) (d): “00000000” Byte of Sync word (only used if Sync_size = 1x) (d): “00000000” Byte of Sync word (only used if Sync_size = 11) (d): “00000000” Page SX1210 www.semtech.com ...
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... Res 1 Rev 2– Sept 8 , 2008 RW Description r/w Clkout control 0 Disabled 1 Enabled, Clk frequency set by Clkout_freq (d) r/w Frequency of the signal provided on CLKOUT: fclkout = if Clkout_freq = “00000” f xtal f = xtal fclkout 2 ⋅ Clkout _ freq (d): 01111 (= 427 kHz) r/w Reserved (d): “00” Page SX1210 otherwise www.semtech.com ...
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... Node_adrs & 0x00 accepted, else rejected. 11 Node_adrs & 0x00 & 0xFF accepted, else rejected. r CRC check result for current packet (READ ONLY): 0 Fail 1 Pass r/w FIFO auto clear if CRC failed for current packet (d) 1 off r/w Reserved (d): “0000000” recommended to set to “1000000” Page SX1210 www.semtech.com ...
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... Key benefits of this are: No hand trimming of the reference frequency required: the actual reference frequency of the Device Under Test (DUT) can be easily measured (e.g. from the CLKOUT output of the SX1210) and the tool will calculate the best frequencies to compensate for the crystal initial error. ...
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... Wait TS FS Set SX1210 in Rx mode Wait for Receiver settling Set SX1210 in FS mode Wait for PLL settling Figure 40: Optimized Rx Cycle Page SX1210 Time SX1210 can be put in Any other mode www.semtech.com ...
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... IDDR 3mA typ IDDFS 1.3mA typ. Wait TS RE SX1210 is now ready for data reception Wait TS HOP 1. Set R2/P2/S2 2. Set SX1210 in FS mode, change MCParam_Band if needed, then switch from R1/P1/S1 to R2/P2/S2 Figure 41: Rx Hop Cycle Page SX1210 Time Set SX1210 back in Rx mode www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.4. Reset of the Chip A power-on reset of the SX1210 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 13. 7.4.1. POR If the application requires the disconnection of VDD from the SX1210, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus ...
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... SAW filter. It has been added for debug purposes could be removed for a direct antenna connection if there bias is expected at the antenna port. Please note that for SX1210 C10 can be replaced a 5.4nH inductor 0Ohm, L3, C4, R1, C8 and C11 are not used. SAW filter is optional on most application (refer toTable 29: Reference Design BOM) 7 ...
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... NPO 5% Multilayer 0.2 nH Wire wound - SAW Filter - - - - - - - - - - - - 5% NPO Page SX1210 Size Comment TQFN-32 - 5.0*3.2 mm Fundamental, Cload=15 pF 0402 Loop filter 0402 VDD decoupling 0402 Top regulator decoupling 0402 Digital regulator decoupling 0402 VCO regulator decoupling 0402 Loop Filter 0402 Loop Filter 0402 DC block and L4 adjust ...
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... Max. drift Programmed Actual kHz kHz +/- ppm 400 306 62 250 214 53 175 158 37 150 137 41 125 116 36 100 96 27 100 Page SX1210 www.semtech.com ...
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... Setting Addr 16 Programmed kbps kHz Hex kHz 117 C1 150 16.67 113 C1 150 12.5 110 A0 125 9.52 108 A0 125 8 105 A0 125 4.76 102 A0 125 2.41 102 A0 125 1.56 th Rev 2– Sept 8 , 2008 Max. drift Actual kHz +/- ppm 154 41 154 46 129 22 129 23 129 27 129 30 129 30 Page SX1210 www.semtech.com ...
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... Figure 47: Sensitivity Across the 868 MHz Band Sensitivity over the Frequency Band 904 906 908 910 912 914 916 918 Frequency [MHz] Sensitivity SAW Ripple Figure 48: Sensitivity Across the 915 MHz Band Page 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 868 869 870 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 920 922 924 926 928 www.semtech.com SX1210 ...
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... Rev 2– Sept 8 , 2008 Sensitivity Loss vs. LO Drift 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -15 - Drift [kHz] Figure 49: FSK Sensitivity Loss vs. LO Drift Sensitivity Loss vs. LO Drift 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -60 -40 - Drift [kHz] Figure 50: OOK Sensitivity Loss vs. LO Drift Page SX1210 100 www.semtech.com ...
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... Sensitivity vs. Receiver BW 1.0 0.0 50 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 1.0 0.0 0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 th Rev 2– Sept 8 , 2008 Sensitivity vs. Fc 100 150 200 Fc of Active Filter [kHz] Figure 51: FSK Sensitivity vs Sensitivity Change vs. (Fc-Fo) 50 100 150 200 Fc-Fo [kHz] Figure 52: OOK Sensitivity Change vs Page SX1210 250 300 250 300 350 www.semtech.com ...
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... The sensitivity performance is very stable over the VDD range, and the effect of high temperature is minimal. 7.6.5. Sensitivity vs. Bit Rate 8.0 6.0 4.0 2.0 0.0 0 -2.0 -4.0 -6.0 -8.0 th Rev 2– Sept 8 , 2008 Sensitivity Stability 2.40 2.70 3.00 VDD [V] Figure 53: Sensitivity Stability Sensitivity Change over Bit Rate [kb/s] Figure 54: FSK Sensitivity vs. BR Page SX1210 3.30 3.60 85°C 25°C 0°C -40°C 75 100 www.semtech.com ...
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... Rev 2– Sept 8 , 2008 Sensitivity Change over the BR 4 6.5 9 11.5 Bit Rate [kbps] Figure 55: OOK Sensitivity vs. BR ACR in FSK Mode -600 -400 -200 0 200 Offset [kHz] Figure 56: ACR in FSK Mode Page SX1210 14 16.5 400 600 800 1000 www.semtech.com ...
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... In OOK mode, the polyphase filter efficiency is limited, thus limiting the adjacent channel rejection at 2xFo distance. th Rev 2– Sept 8 , 2008 ACR in OOK Mode -200 -100 0 -10 -20 Offset [kHz] Figure 57: ACR in OOK Mode Page SX1210 100 200 300 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 8. Packaging Information 8.1. Package Outline Drawing SX1210 is available in a 32-lead TQFN package as shown in Figure 58 below. 8.2. PCB Land Pattern th Rev 2– Sept 8 , 2008 Figure 58: Package Outline Drawing Figure 59: PCB Land Pattern Page SX1210 www.semtech.com ...
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... Notes: *all dimensions in mm *single sprocket holes th Rev 2– Sept 8 , 2008 Direction of Feed Reel Reel Reel Ao/Bo Ko Size Width 5.25 1.10 330.2 12.4 +/-0.2 +/-0.1 Figure 60: Tape & Reel Dimensions Page SX1210 Min. Min.Trail QTY per Leader er Length Reel Length 400 400 3000 www.semtech.com ...
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... Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. th Rev 2– Sept 8 , 2008 Semtech Corporation 200 Flynn Road, Camarillo, CA 93012 Page SX1210 www.semtech.com ...