SI4702-C19-GM Silicon Laboratories Inc, SI4702-C19-GM Datasheet - Page 18

• Manufacturer Part Number: SI4702-C19-GM
• Description: IC FM RADIO TUNER 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4702-C19-GM

• Package / Case: 20-QFN
• Frequency: 76MHz ~ 108MHz
• Modulation Or Protocol: FM
• Applications: Cellular, MP3, PDAs, Portable Radios
• Current - Receiving: 14.4mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Bus Type: 2-Wire, 3-Wire
• Maximum Frequency: 108 MHz
• Minimum Frequency: 76 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: Radio
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 20 C
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1738

Si4702/03-C19
For additional recommendations on optimizing the seek
function,
Adjustability and Settings."
4.7. Reference Clock
The Si4702/03-C19 accepts a 32.768 kHz reference
clock to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
“DC Characteristics
voltage
Characteristics," on page 12 for frequency tolerance
information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to 2. "Typical Application
Schematic" on page 14. The oscillator must be enabled
or disabled while in powerdown (ENABLE = 0) as shown
in Figure 9, “Initialization Sequence,” on page 21.
Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown. Note that RCLK voltage levels are
not specified. The typical RCLK voltage level, when the
crystal oscillator is used, is 0.3 V
4.7.1. Si4702/03-C19 Internal Crystal Oscillator
The Si4702/03-C19 seek/tune performance may be
affected by data activity on the SDIO bus when using
the integrated internal oscillator. SDIO activity results
from polling the tuner for status or communicating with
other devices that share the SDIO bus. If there is SDIO
bus activity while the Si4702/03-C19 is performing the
seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops.
SDIO activity during all other operational states does
not affect performance.
For
recommends that all SDIO data traffic be suspended
during Si4702/03-C19 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Please refer to Sections 4.6. "Tuning" on page 17 and 5.
"Register Summary" on page 22 for specified seek/tune
times and register use guidelines.
The layout guidelines in Si4700/01/02/03 Evaluation
Board User’s Guide, Section 8.3 Si4702/03-C19
Daughter Card should be followed to help ensure robust
FM performance.
Please refer to the posted Si4702/03 Internal Crystal
Oscillator Errata for more information.
18
best seek/tune
Errata
levels
consult
1
and
"AN284:
,” on page 5 for input switching
results,
Table 8,
Si4700/01/02/03
pk-pk
Silicon
.
"FM
Laboratories
Receiver
Seek
Rev. 1.1
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V
is applied regardless of the state of the V
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN pin is sampled low by the device on a rising SCLK
edge. The control word is latched internally on rising
SCLK edges and is nine bits in length, comprised of a
four bit chip address A7:A4 = 0110b, a read/write bit
(write = 0 and read = 1), and a four bit register address,
A3:A0. The ordering of the control word is A7:A5, R/W,
A4:A0. Refer to Section 5. "Register Summary" on page
22 for a list of all registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 8, Figure 3, “3-Wire Control Interface Write Timing
Parameters,” on page 8, and Figure 4, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.8.2. 2-wire Control Interface
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
IO
D
supply
or V
A