ATA3745P3-TGQY Atmel, ATA3745P3-TGQY Datasheet - Page 14

• Manufacturer Part Number: ATA3745P3-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3745P3-TGQY

• Frequency: 310MHz ~ 440MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA3745P3-TGQYTR

Figure 5-5.
Figure 5-6.
Figure 5-7.
14
ATA3745
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
Bit check
Dem_out
counter
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
Bit check
Dem_out
counter
Timing Diagram During Bit Check
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check
Dem_out
counter
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Startup mode
Start up mode
T
Figure
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
period. When the bit check becomes active, the bit check counter is clocked with the cycle
T
Figure 5-5
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails
if CV_Lim reaches Lim_max. This is illustrated in
Startup
0
XClk
0
0
.
5-5,
1 2
1 2
1 2
shows how the bit check proceeds if the bit-check counter value CV_Lim is within
3 4
Figure 5-6
3 4
3 4
T
5 6
XCLK
5 6
5 6
Bit check mode
Startup
7 8
1
7 1
2 3
1 2
2 3
. The output of the demodulator (Dem_out) is undefined during that
and
4 5
3 4
1/2 Bit
4 5
6 7
5 6
Figure 5-7
Bit check mode
6 7
8
7 8
Bit check failed (CV_Lim_ < Lim_min)
1/2 Bit
9 10
8
9 10
9 10
1/2 Bit
11 12
11 12
11 12
illustrate the bit check for the default bit check limits
13 14
13 14
15 16
Bit check ok
15 16
Lim_max)
17 18
17 18
Bit check failed (CV_Lim_
Figure 5-8 on page
19 20
1 2
0
Sleep mode
21 22
3 4
23 24
5 6
1/2 Bit
7 8
9 10
11 12
Sleep mode
Lim_max)
0
15.
Bit check ok
13 14
15
1 2
1/2 Bit
3 4
4901B–RKE–11/07
Figure
5-7,