ADF7025BCPZ Analog Devices Inc, ADF7025BCPZ Datasheet - Page 15
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ADF7025BCPZ
Manufacturer Part Number
ADF7025BCPZ
Description
IC ASK/FSK TXRX 928MHZ 48-LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.ADF7025BCPZ.pdf
(44 pages)
Specifications of ADF7025BCPZ
Frequency
431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
Data Rate - Maximum
384kbps
Modulation Or Protocol
FSK
Applications
Keyless Entery, Home Automation, Wireless Audio/Video
Power - Output
-20dBm ~ 13dBm
Sensitivity
-104dBm
Voltage - Supply
2.3 V ~ 3.6 V
Current - Receiving
19mA
Current - Transmitting
28mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LFCSP
Receiving Current
21mA
Transmitting Current
19.3mA
Data Rate
384Kbps
Frequency Range
431MHz To 928MHz
Modulation Type
FSK
Rf Ic Case Style
LFCSP
No. Of Pins
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF7025BCPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FREQUENCY SYNTHESIZER
REFERENCE INPUT SECTION
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected by adjusting the Fractional-N
value (see the N Counter section). A single-ended reference
(TCXO, CXO) can also be used. The CMOS levels should be
applied to OSC2 with R1_DB12 set low.
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 19, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB [8:11]. On power-up, the CLKOUT defaults to
divide-by-8.
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at F
OSC1
Figure 19. Oscillator Circuit on the ADF7025
OSC1
DIVIDER
1 TO 15
Figure 20. CLKOUT Stage
CP2
CP1
÷2
OSC2
DV
DD
CLK
.
CLKOUT
CLKOUT
ENABLE BIT
Rev. A | Page 15 of 44
R Counter
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The divide
ratio is set in Register 1. Maximizing the PFD frequency reduces
the N value. This reduces the noise multiplied at a rate of 20 log(N)
to the output, as well as reducing occurrences of spurious
components. The R register defaults to R = 1 on power-up.
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
points in the ADF7025. The state of MUXOUT is controlled by
Bits R0_DB [29:31].
Regulator Ready
Regulator ready is the default setting on MUXOUT after the
transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is powered
from the regulator, the regulator must be at its nominal voltage
before the ADF7025 can be programmed. The status of the
regulator can be monitored at MUXOUT. When the
regulator_ready signal on MUXOUT is high, programming of
the ADF7025 can begin.
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until a 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
REGULATOR READY
PFD [Hz] = XTAL/R
PLL TEST MODES
Σ-∆ TEST MODES
Figure 21. MUXOUT Circuit
MUX
CONTROL
DGND
DV
ADF7025
DD
MUXOUT